Variable resistance memory with lattice array using enclosing transistors

Patent metadata

Field	Value
Publication number	US-11763885-B2
Application number	US-202117348194-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Apr 3, 2007
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

First claim

The invention claimed is:

1. An apparatus, comprising:
a first word line extending along a first direction of an array, wherein the first word line comprises a repeating pattern of a first set of enclosures;
a first set of memory elements, each memory element of the first set of memory elements formed on and coupled with a respective contact that is enclosed by a respective enclosure of the first set of enclosures;
a bitline extending along the first direction and disposed adjacent to the first word line; and
a first select line extending along a second direction perpendicular to the first direction, the first select line electrically connected with a first memory element of the first set of memory elements, a second memory element of a second set of memory elements, and a third memory element of a third set of memory elements such that the first select line has a wavy pattern, wherein the second memory element is diagonally adjacent to the first memory element and the third memory element.

2. The apparatus of claim 1 , further comprising:
a second word line extending along the first direction of the array, wherein the second word line comprises a repeating pattern of a second set of enclosures, each memory element of the second set of memory elements formed on and coupled with a respective contact that is enclosed by a respective enclosure of the second set of enclosures.

3. The apparatus of claim 2 , wherein the repeating pattern of the first set of enclosures and the repeating pattern of the second set of enclosures each form a diamond lattice pattern.

4. The apparatus of claim 3 , wherein the first word line is offset from the second word line along the first direction such that peaks of the diamond lattice pattern of the first word line are at least partially disposed within valleys of the diamond lattice pattern of the second word line.

5. The apparatus of claim 2 , wherein the bitline curves between the first word line and the second word line.

6. The apparatus of claim 1 , wherein the first memory element is formed on and coupled with a first respective contact, and wherein an enclosure of the first set of enclosures forms a structure around the first respective contact, the structure comprising three or more transistors adjacent to the first respective contact.

7. The apparatus of claim 1 , wherein the repeating pattern of the first set of enclosures forms a diamond lattice pattern, and wherein the bitline comprises a pattern of bitline contacts, wherein each bitline contact of the pattern of bitline contacts is located at a respective peak of the diamond lattice pattern.

8. The apparatus of claim 6 , wherein the structure is a diamond structure comprising four transistors.

9. The apparatus of claim 6 , wherein the structure is a triangular structure comprising three transistors.

10. An apparatus, comprising:
a memory array, comprising:
a first memory element, a second memory element, and a third memory element, wherein the second memory element is diagonally adjacent to the first memory element and the third memory element;

a word line extending along a first direction of the memory array, the word line comprising a repeating pattern of a set of enclosures, wherein the first memory element is formed on and coupled with a first contact that is enclosed by an enclosure of the set of enclosures;
a bitline extending along the first direction and disposed adjacent to the word line; and
a select line extending along a second direction perpendicular to the first direction, the select line electrically connected with the first memory element, the second memory element, and the third memory element such that the select line has a wavy pattern.

11. The apparatus of claim 10 , further comprising a set of memory elements respectively formed on and coupled with a set of contacts, wherein the set of memory elements includes the first memory element and the set of contacts includes the first contact, wherein each contact of the set of contacts is respectively enclosed by an enclosure of the set of enclosures.

12. The apparatus of claim 10 , wherein an enclosure of the set of enclosures forms a structure around the first contact, the structure comprising three or more transistors adjacent to the first contact.

13. The apparatus of claim 12 , wherein the structure is a diamond structure comprising four transistors.

14. The apparatus of claim 12 , wherein the structure is a triangular structure comprising three transistors.

15. The apparatus of claim 10 , further comprising a second word line extending along the first direction, the second word line comprising a repeating pattern of a second set of enclosures, wherein the second memory element is formed on and coupled with a second contact that is enclosed by a second enclosure of the second set of enclosures.

16. The apparatus of claim 15 , wherein the repeating pattern of the set of enclosures and the repeating pattern of the second set of enclosures each form a diamond lattice pattern.

17. The apparatus of claim 15 , wherein the repeating pattern of the set of enclosures and the repeating pattern of the second set of enclosures each form a triangular lattice pattern.

18. The apparatus of claim 15 , further comprising:
a first set of memory elements respectively formed on and coupled with a first set of contacts, wherein the first set of memory elements includes the first memory element and the first set of contacts includes the first contact, wherein each contact of the first set of contacts is respectively enclosed by an enclosure of the set of enclosures; and
a second set of memory elements respectively formed on and coupled with a second set of contacts, wherein the second set of memory elements includes the second memory element and the second set of contacts includes the second contact, wherein each contact of the second set of contacts is respectively enclosed by an enclosure of the second set of enclosures.

19. The apparatus of claim 15 , further comprising a third word line extending along the first direction, the third word line comprising a repeating pattern of a third set of enclosures, wherein the third memory element is formed on and coupled with a third contact that is enclosed by a third enclosure of the third set of enclosures.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Liu Jun

Classifications

• H10F99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C16/02 Primary

  electrically programmable · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title