Apparatus and method for handling a data error in a memory system

Patent metadata

Field	Value
Publication number	US-11762734-B2
Application number	US-202016915407-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Jan 17, 2020
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A memory system includes a memory device and a controller. The memory device is configured to supply a read voltage into a plurality of non-volatile memory cells and transfer values obtained from the plural non-volatile memory cells. The controller is coupled to the memory device via at least one channel. The controller adjusts a level of the read voltage based on a cell difference probability (CDP) calculated from the values when a read operation to the plurality of non-volatile memory cells fails.

First claim

What is claimed is:

1. A memory system, comprising:
a memory device configured to supply a read voltage into a plurality of non-volatile memory cells and output values obtained from the plurality of non-volatile memory cells; and
a controller, coupled to the memory device via at least one channel, configured to:
calculate cell difference probabilities (CDPs) regarding neighboring values among the values, each CDP indicating a ratio of a specific scanned value between the neighboring values, before decoding the specific scanned value, when the read voltage corresponding to the specific scanned value is applied, after a read operation to the plurality of non-volatile memory cells fails;
determine change direction and level of the read voltage based on the cell difference probabilities (CDPs);
adjust a level of the read voltage based on the change direction and level of the read voltage; and
perform different types of decision decoding to recover the data stored in the plurality of non-volatile memory cells based on a comparison result of the cell difference probabilities (CDPs) and a first reference.

2. The memory system according to claim 1 ,
wherein the controller is configured to perform a hard decision decoding to recover data stored in the plurality of non-volatile memory cells when one of the cell difference probabilities (CDPs) is equal to or greater than the first reference.

3. The memory system according to claim 2 ,
wherein the controller is further configured to perform the soft decision decoding to recover the data stored in the plurality of non-volatile memory cells when one of the cell difference probabilities (CDPs) is less than the first reference.

4. The memory system according to claim 3 ,
wherein the controller is further configured to perform the soft decision decoding on at least one of other values among the values to recover the data stored in the plurality of non-volatile memory cells, when the cell difference probability (CDP) regarding the at least one of the other values among the values outputted from the memory device after the level of read voltage is adjusted.

5. The memory system according to claim 2 ,
wherein the controller is further configured to increase or decrease the level of the read voltage by a preset level when a count of unsatisfied check nodes is equal to or less than a second reference.

6. The memory system according to claim 2 ,
wherein the controller is further configured to either perform a soft decision decoding based on a read voltage having a prescribed level or check a propriety of the first reference, when the count of unsatisfied check nodes is equal to or less than the second reference.

7. The memory system according to claim 2 ,
wherein one of the cell difference probabilities (CDPs) indicates whether a voltage distribution based on at least one of the values before decoding the at least one of the values falls within a range determined by a preset ratio of the maximum/minimum levels regarding a threshold voltage of each non-volatile memory cell.

8. The memory system according to claim 1 ,
wherein the controller is further configured to:
store a history regarding a scan operation performed after the read voltage is searched; and
compare one of the cell difference probabilities (CDPs) with a first reference based on the history.

9. The memory system according to claim 8 ,
wherein the controller is further configured to perform a soft decision decoding on the values before the scan operation is performed after the read voltage is searched.

10. The memory system according to claim 8 ,
wherein the controller is further configured to remove, in the history, a case when the read voltage is adjusted by a read retry operation.

11. A method for operating a memory system, comprising:
supplying a read voltage to a plurality of non-volatile memory cells to perform a read operation regarding values stored in the plurality of non-volatile memory cells;
calculating cell difference probabilities (CDPs) regarding neighboring values among the values read from the plurality of non-volatile memory cells, each CDP indicating a ratio of a specific scanned value, before decoding the specific scanned value, between the neighboring values when the read voltage corresponding to the specific scanned value is applied, after the read operation has failed;
determining change direction and level of the read voltage based on the cell difference probabilities (CDPs);
adjusting the read voltage based on the change direction and level of the read voltage; and
performing different types of decision decoding to recover the data stored in the plurality of non-volatile memory cells based on a comparison result of the cell difference probabilities (CDPs) and a first reference.

12. The method according to claim 11 , wherein the adjusting the read voltage comprises:
performing a hard decision decoding to recover data stored in the plurality of non-volatile memory cells when one of the CDPs is equal to or larger than the first reference.

13. The method according to claim 12 , wherein the adjusting the read voltage further comprises:
performing the soft decision decoding to recover the data stored in the plurality of non-volatile memory cells when one of the CDPs is less than the first reference.

14. The method according to claim 13 , wherein the adjusting the read voltage further comprises:
performing the soft decision decoding on at least one of other values among the values to recover the data stored in the plurality of non-volatile memory cells, when the CDP regarding the at least one of the other values among the values outputted from the memory device after the level of read voltage is adjusted.

15. The method according to claim 12 , further comprising:
increasing or decreasing the level of the read voltage by a preset level when a count of unsatisfied check nodes is equal to or less than a second reference.

16. The method according to claim 15 , further comprising:
when the count of unsatisfied check nodes is equal to or less than the second reference, either performing a soft decision decoding based on a read voltage having a prescribed level or checking a propriety of the first reference.

17. The method according to claim 11 ,
wherein one of the CDPs indicates whether a voltage distribution based on at least one of the values before decoding the at least one of the values falls within a range determined by a preset ratio of the maximum/minimum levels regarding a threshold voltage of each non-volatile memory cell.

18. The method according to claim 11 , further comprising:
storing a history regarding a scan operation performed after the read voltage is searched; and
comparing one of the CDPs with a first reference based on the history.

19. The method according to claim 18 , further comprising:
performing a soft decision decoding on the values before the scan operation is performed after the read voltage is searched.

20. The method according to claim 18 , further comprising:
removing, in the history, a case where the read voltage is adjusted by a read retry operation.

Assignees

• Sk Hynix Inc

Inventors

• Lee Jaeyoon

Classifications

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/1441 Primary

  Resetting or repowering · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title