Accessing registers of fluid ejection devices

Patent metadata

Field	Value
Publication number	US-11760085-B2
Application number	US-201916768046-A
Country	US
Kind code	B2
Filing date	Feb 6, 2019
Priority date	Feb 6, 2019
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

An integrated circuit to drive a plurality of fluid actuation devices includes a configuration register, a plurality of interfaces, and control logic. The plurality of interfaces include a mode interface and a data interface. The control logic enables writing to the configuration register in response to a signal on the mode interface transitioning to logic high with a logic high signal on the data interface.

First claim

The invention claimed is:

1. An integrated circuit for a fluid ejection device, the integrated circuit comprising:
a configuration register;
a plurality of interfaces comprising a mode interface, a fire interface, and a data interface; and
control logic to enable writing to the configuration register in response to a signal on a single mode interface transitioning from logic low to logic high with a logic high signal on a single data interface during the single mode interface transition from logic low to logic high, and a logic low signal on the fire interface,
wherein the single data interface is to input data to the integrated circuit and output data from the integrated circuit.

2. The integrated circuit of claim 1 , wherein the control logic is to disable writing to the configuration register in response to a logic low signal on the single mode interface.

3. The integrated circuit of claim 1 , wherein the configuration register is to receive serial data from the single data interface with the configuration register enabled for writing.

4. The integrated circuit of claim 3 , wherein the plurality of interfaces comprises a clock interface, and
wherein the configuration register is to receive the serial data from the single data interface aligned with a clock signal from the clock interface.

5. The integrated circuit of claim 1 , wherein the integrated circuit is a fluid ejection die.

6. The integrated circuit of claim 1 , wherein the configuration register stores data for testing the integrated circuit, detecting cracks within a substrate of the integrated circuit, enabling watchdogs of the integrated circuit, setting analog delays of the integrated circuit, or enabling access to memory of the integrated circuit.

7. The integrated circuit of claim 1 , wherein the integrated circuit comprises a status register, and
wherein the control logic is to enable reading of the status register in response to both the signal on the single mode interface transitioning to logic high with a logic high signal on the single data interface and transitioning the signal on the fire interface to logic high with the signal on the single data interface floating.

8. The integrated circuit of claim 7 , wherein the control logic is to disable reading of the status register in response to a logic low signal on the single mode interface.

9. The integrated circuit of claim 7 , wherein the control logic is to disable reading of the status register in response to a logic low signal on the fire interface.

10. The integrated circuit of claim 7 , wherein the status register is to output serial data to the single data interface with the status register enabled for reading.

11. The integrated circuit of claim 10 , wherein the plurality of interfaces comprises a clock interface, and
wherein the status register is to output serial data to the single data interface aligned with a clock signal on the clock interface.

12. A method for accessing a fluid ejection device, the method comprising:
setting a signal on a single data contact pad of the fluid ejection device to logic high;
setting a signal on a single fire contact pad of the fluid ejection device to logic low;
transitioning a signal on a single mode contact pad of the fluid ejection device from logic low to logic high; and
enabling writing to a configuration register of the fluid ejection device in response to transitioning the signal on the single mode contact pad from logic low to logic high with the signal on the single data contact pad logic high during the transition of the signal on the single mode contact pad from logic low to logic high, and the signal on the single fire contact pad logic high,
wherein the single data contact pad is to input data to the fluid ejection device and output data from the fluid ejection device.

13. The method of claim 12 , further comprising:
transitioning the signal on the single mode contact pad to logic low; and
disabling writing to the configuration register in response to the logic low signal on the single mode contact pad.

14. The method of claim 12 , further comprising:
with the configuration register enabled for writing, applying a serial data signal to the single data contact pad to write the serial data to the configuration register.

15. The method of claim 14 , further comprising:
with the configuration register enabled for writing, applying the serial data signal to the single data contact pad aligned with a clock signal on a clock contact pad of the fluid ejection device.

16. The method of claim 12 , wherein the configuration register stores data for testing the fluid ejection device, detecting cracks within a substrate of the fluid ejection device, enabling watchdogs of the fluid ejection device, setting analog delays of the fluid ejection device, or enabling access to memory of the fluid ejection device.

Assignees

• Hewlett Packard Development Co

Inventors

• Linn Scott A
• Gardner James Michael
• Cumbie Michael W

Classifications

• B41J2/04523 Primary

  reducing size of the apparatus · CPC title

• B41J2/0458 Primary

  controlling heads based on heating elements forming bubbles · CPC title

• B41J2/04541 Primary

  Specific driving circuit · CPC title

• B41J2/04551

  using several operating modes · CPC title

• B41J2/04586

  controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type · CPC title