Device for generating radiofrequency signals in phase quadrature

US11757477B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11757477-B2
Application numberUS-202117187024-A
CountryUS
Kind codeB2
Filing dateFeb 26, 2021
Priority dateFeb 27, 2020
Publication dateSep 12, 2023
Grant dateSep 12, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a first mixer module comprising: a voltage/current transconductor stage comprising: first transistors; a polarization circuit including two first resistors respectively connected between gates of the first transistors and a polarization input configured to receive an adjustable polarization bias voltage for setting of a current circulating in the first transistors; a first current amplifier block having a first capacitor connected between a gate of a first one of the first transistors and a gate of a third transistor, and a second resistor coupled between the gate of the third transistor and a drain of the third transistor; and a second current amplifier block having a second capacitor connected between a gate of a second one of the first transistors and a gate of a fourth transistor, and a third resistor coupled between the gate of the fourth transistor and a drain of the fourth transistor; and a mixing stage connected to the voltage/current transconductor stage, the mixing stage comprising: second transistors; a resistive degeneration circuit connected to sources of the second transistors; and a calibration input connected to gates of the second transistors and configured to receive an adjustable calibration voltage, wherein sources of the first transistors are directly connected to a cold power supply point; and a calibration circuit configured to adjust the adjustable calibration voltage in accordance with at least a phase of outputs of the second transistors. 2. The electronic device according to claim 1 , wherein: the third transistor of the first current amplifier block has a source connected to a power supply terminal and a drain connected to a drain of the first one of the first transistors; and the fourth transistor of the second current amplifier block has a source connected to the power supply terminal and a drain connected to a drain of the second one of the first transistors. 3. The electronic device according to claim 1 , wherein the transconductor stage further comprises a first input interface including two first input terminals respectively connected to gates of two first transistors; and wherein the mixing stage further comprises: a second input interface including two second input terminals respectively connected to the gates of two pairs of the second transistors; and an output interface including two output terminals, each output terminal being connected to two of the second transistors belonging to two different pairs. 4. The electronic device according to claim 3 , wherein the two first input terminals are configured to respectively receive two first signals having sinusoidal shapes offset by 180°, wherein the two second input terminals are configured to respectively receive two second signals having sinusoidal shapes offset by 180°, and wherein the two second signals are either identical to the two first signals or offset by 90° with respect to the two first signals. 5. The electronic device according to claim 4 , further comprising: a signal generator having two first generation terminals configured to generate two first sinusoidal signals offset by 180° and two second generation terminals configured to generate two first cosinusoidal signals offset by 180°, the first sinusoidal and first cosinusoidal signals having a same initial frequency; the first mixer module, including two first mixer input terminals and two second mixer input terminals respectively connected to the two first generation terminals; a second mixer module, including two third mixer input terminals and two fourth mixer input terminals respectively connected to the two second generation terminals; wherein two output terminals of the first mixer module are respectively connected to two opposite output terminals of the second mixer module, thereby forming two first output nodes configured to generate two second cosinusoidal signals offset by 180° having a frequency double the initial frequency; a third mixer module, including two fifth mixer input terminals respectively connected to the two first generation terminals, and two sixth mixer input terminals respectively connected to the two second generation terminals; and a fourth mixer module, including two seventh mixer input terminals respectively connected to the two second generation terminals, and two eight mixer input terminals respectively connected to the two first generation terminals; wherein two output terminals of the third mixer module are respectively connected to two homologous output terminals of the fourth mixer module, thereby forming two second output nodes configured to generate two second sinusoidal signals offset by 180° having a frequency double the initial frequency. 6. The electronic device according to claim 5 , wherein the signal generator comprises: a signal source configured to generate an initial signal having a sinusoidal shape having the initial frequency; and a polyphase filter connected between an output of the signal source and the first and second generation terminals; and wherein the electronic device further comprises a voltage-amplification circuit connected between each second terminal of each mixer module and a corresponding one of the generation terminals. 7. The electronic device according to claim 5 , wherein the calibration circuit is configured to adjust the adjustable calibration voltage according to a phase shift between the second sinusoidal and second cosinusoidal signals generated at the first and second output nodes. 8. The electronic device according to claim 5 , wherein the initial frequency is greater than or equal to 10 GHz. 9. The electronic device according to claim 8 , wherein the initial frequency is equal to 14 GHz. 10. A communication apparatus comprising: a signal generator having two first generation terminals configured to generate two first sinusoidal signals offset by 180° and two second generation terminals configured to generate two first cosinusoidal signals offset by 180°, the first sinusoidal and first cosinusoidal signals having a same initial frequency; a first mixer module, including two first input terminals and two second input terminals respectively connected to the two first generation terminals; a second mixer module, including two third input terminals and two fourth input terminals respectively connected to the two second generation terminals; wherein two output terminals of the first mixer module are respectively connected to two opposite output terminals of the second mixer module, thereby forming two first output nodes configured to generate two second cosinusoidal signals offset by 180° having a frequency double the initial frequency; a third mixer module, including two fifth input terminals respectively connected to the two first generation terminals, and two sixth input terminals respectively connected to the two second generation terminals; a fourth mixer module, including two seventh input terminals respectively connected to the two second generation terminals, and two eighth input terminals respectively connected to the two first generation terminals; wherein two output terminals of the third mixer module are respectively connected to two homologous output terminals of the fourth mixer module, thereby forming two second output nodes configured to generate two second sinusoidal signals offset by 180° having a frequency double the initial frequency; wherein each mixer module comprises: a mixing stage comprising: second transistors; a resistive degeneration circuit connected to sources of the second transistors; and a calibration input connected to gates of the second transistors an

Assignees

Inventors

Classifications

  • H03B19/14Primary

    by means of a semiconductor device · CPC title

  • H04B1/0096Primary

    where a full band is frequency converted into another full band · CPC title

  • Gilbert multipliers · CPC title

  • using field-effect transistors (H03D7/145 takes precedence) · CPC title

  • Double balanced arrangements, i.e. where both input signals are differential · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11757477B2 cover?
An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors…
Who is the assignee on this patent?
St Microelectronics Alps Sas
What technology area does this patent fall under?
Primary CPC classification H03B19/14. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).