Manufacturing method for surface acoustic wave filter package structure

Patent metadata

Field	Value
Publication number	US-11757426-B2
Application number	US-202217833086-A
Country	US
Kind code	B2
Filing date	Jun 6, 2022
Priority date	Nov 9, 2018
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A surface acoustic wave (SAW) filter package structure includes a dielectric substrate having a dielectric layer, a first patterned conductive layer, a second patterned conductive layer, and a conductive connection layer. The conductive connection layer is electrically connected between the first patterned conductive layer and the second patterned conductive layer, which are disposed at opposite sides of the dielectric layer. The second patterned conductive layer has a finger electrode portion. An active surface of a chip is faced toward the finger electrode portion. A polymer sealing frame is disposed between the chip and the dielectric substrate and surrounds the periphery of the chip to form a chamber together with the chip and the dielectric substrate. The mold sealing layer is disposed on the dielectric substrate and covers the chip and the polymer sealing frame. A manufacturing method of the SAW filter package structure is also disclosed.

First claim

What is claimed is:

1. A manufacturing method for surface acoustic wave filter package structure, comprising:
forming a dielectric substrate with a first side and a second side on a carrier board, wherein the dielectric substrate has a first patterned conductive layer, a dielectric layer, a conductive connection layer, and a second patterned conductive layer;
forming a plurality of polymer sealing frames on the second side of the dielectric substrate, wherein each of the polymer sealing frames has an opening to partially expose out of the dielectric substrate;
arranging a plurality of the chips onto corresponding polymer sealing frames, wherein, an active surface of each of the plurality of the chips faces toward the second side of the dielectric substrate, and corresponds to the respective opening of the polymer sealing frame to form a closed cavity by the corresponding polymer sealing frame, the chip and the dielectric substrate;
forming a mold sealing layer to cover the plurality of chips and the plurality of polymer sealing frames, and a side of the plurality of polymer sealing frames is exposed out of the mold sealing layer; and
removing the carrier board.

2. The manufacturing method of claim 1 , wherein the step of forming the dielectric substrate, comprising:
arranging the first patterned conductive layer on one surface of the carrier board;
arranging the dielectric layer on the carrier board to cover the first patterned conductive layer;
forming a plurality of openings on the dielectric layer to partially expose the first patterned conductive layer; and
arranging the second patterned conductive layer on the dielectric layer and the conductive connection layer, and the second patterned conductive layer at least has a conductive circuit portion, a conductive electrode portion and a finger electrode portion.

3. The manufacturing method of claim 2 , wherein after arranging the second patterned conductive layer, further comprising:
arranging another dielectric layer on the dielectric substrate and the second patterned conductive layer, and exposure out of one surface of the second patterned conductive layer.

4. The manufacturing method of claim 1 , wherein after removal of the carrier board, further comprising:
arranging a patterned protective layer on the first side of the dielectric substrate and partial exposure out of the first patterned conductive layer.

5. The manufacturing method of claim 1 , wherein before or after the removal of the carrier board, further comprising:
cutting according to an area of the plurality of chips and the plurality of polymer sealing frames to form a plurality of single package structure.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping
• Hsu Che-Wei

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title