Oscillator circuit

Patent metadata

Field	Value
Publication number	US-11757405-B2
Application number	US-202217733158-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Oct 31, 2019
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

An oscillator circuit includes an amplifier including a first transconductance amplifier and a second transconductance amplifier; and a resonator including a capacitor element and an inductor element. The capacitor element includes a first capacitor and a second capacitor, the inductor element includes a tapped inductor, the tapped inductor includes a first segment of inductor and a second segment of inductor, and the first segment of inductor and the second segment of inductor are coupled using the first capacitor. The first segment of inductor includes a first terminal and a second terminal coupled to an input terminal and an output terminal of the first transconductance amplifier respectively. The second segment of inductor includes a third terminal and a fourth terminal coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively.

First claim

What is claimed is:

1. An oscillator circuit, comprising:
an amplifier comprising:
a first transconductance amplifier comprising:
a first input terminal; and
a first output terminal; and

a second transconductance amplifier comprising:
a second input terminal; and
a second output terminal; and

a resonator comprising:
a capacitor element comprising:
a first capacitor; and
a second capacitor; and

an inductor element comprising a tapped inductor that comprises:
a first segment of inductor comprising:
a first terminal coupled to the first input terminal;
a second terminal coupled to the first output terminal; and
a fifth terminal;

a second segment of inductor and comprising:
a third terminal coupled to the second input terminal;
a fourth terminal coupled to the second output terminal and further coupled to the first terminal using the second capacitor and
a sixth terminal,
wherein the first terminal and the fourth terminal are output terminals of the tapped inductor,
wherein the second terminal and the third terminal are tap terminals of the tapped inductor, and
wherein the fifth terminal and the sixth terminal are coupled using the first capacitor.

2. The oscillator circuit of claim 1 , wherein the tapped inductor further comprises a plurality of conductive segments that constitute an 8-shaped physical loop through layer-hopping crossing.

3. The oscillator circuit of claim 2 , wherein the conductive segments are configured to be separately cabled at a topmost metal layer of a chip and a second topmost metal layer of the chip.

4. The oscillator circuit of claim 3 , wherein the conductive segments comprise a non-crossing part and two cross parts, wherein the non-crossing part and a first of the two cross parts are configured to be cabled at the topmost metal layer, and wherein a second of the two cross parts is configured to be cabled at the second topmost metal layer.

5. The oscillator circuit of claim 1 , wherein two tap segments corresponding to the second terminal and the third terminal are cabled in a middle of the tapped inductor.

6. The oscillator circuit of claim 1 , wherein an input voltage of the amplifier is configured to exceed a supply voltage of the amplifier.

7. The oscillator circuit of claim 1 , wherein each of the first transconductance amplifier and the second transconductance amplifier comprises an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor, wherein a source of the PMOS transistor is configured to couple to a positive supply rail, wherein gates of the NMOS transistor and the PMOS transistor are coupled as a third input terminal, wherein drains of the NMOS transistor and the PMOS transistor are coupled as a third output terminal, and wherein a source of the NMOS transistor is configured to couple to a ground terminal.

8. The oscillator circuit of claim 1 , wherein the second segment of inductor is coupled to the first segment of inductor using the first capacitor.

9. The oscillator circuit of claim 2 , wherein the conductive segments are configured to be separately cabled at a topmost metal layer of a chip and a redistribution layer located between the chip and a package.

10. The oscillator circuit of claim 9 , wherein the conductive segments comprise a non-crossing part and two cross parts, wherein the non-crossing part and a first of the two cross parts are configured to be cabled at the topmost metal layer, and wherein a second of the two cross parts is configured to be cabled at the redistribution layer.

11. A computer program product comprising computer-executable instructions that are stored on a non-transitory computer-readable medium and that, when executed by a processor, cause an apparatus to produce an oscillator circuit comprising:
an amplifier comprising:
a first transconductance amplifier comprising:
a first input terminal; and
a first output terminal; and

a second transconductance amplifier comprising:
a second input terminal; and
a second output terminal; and

a resonator comprising:
a capacitor element comprising:
a first capacitor; and
a second capacitor; and

an inductor element comprising a tapped inductor that comprises:
a first segment of inductor comprising:
a first terminal coupled to the first input terminal;
a second terminal coupled to the first output terminal; and
a fifth terminal;

a second segment of inductor comprising:
a third terminal coupled to the second input terminal;
a fourth terminal coupled to the second output terminal and further coupled to the first terminal using the second capacitor; and
a sixth terminal,
wherein the first terminal and the fourth terminal are output terminals of the tapped inductor,
wherein the second terminal and the third terminal are tap terminals of the tapped inductor, and
wherein the fifth terminal and the sixth terminal are coupled using the first capacitor.

12. The computer program product of claim 11 , wherein the tapped inductor further comprises a plurality of conductive segments that constitute an 8-shaped physical loop through layer-hopping crossing.

13. The computer program product of claim 12 , wherein the conductive segments are configured to be separately cabled at a topmost metal layer of a chip and a second topmost metal layer of the chip.

14. The computer program product of claim 13 , wherein the conductive segments comprise a non-crossing part and two cross parts, wherein the non-crossing part and a first of the two cross parts are configured to be cabled at the topmost metal layer, and wherein a second of the two cross parts is configured to be cabled at the second topmost metal layer.

15. The computer program product of claim 12 , wherein the conductive segments are configured to be separately cabled at a topmost metal layer of a chip and a redistribution layer located between the chip and a package.

16. The computer program product of claim 15 , wherein the conductive segments comprise a non-crossing part and two cross parts, wherein the non-crossing part and a first of the two cross parts are configured to be cabled at the topmost metal layer, and wherein a second of the two cross parts is configured to be cabled at the redistribution layer.

17. The computer program product of claim 11 , wherein two tap segments corresponding to the second terminal and the third terminal are cabled in a middle of the tapped inductor.

18. The computer program product of claim 11 , wherein an input voltage of the amplifier is configured to exceed a supply voltage of the amplifier.

19. The computer program product of claim 11 , wherein each of the first transconductance amplifier and the second transconductance amplifier comprises an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor, wherein a source of the PMOS transistor is configured to couple to a positive supply rail, wherein gates of the NMOS transistor and the PMOS transistor are coupled as a third input terminal, wherein drains of the NMOS transistor and the PMOS transistor are coupled as a third output terminal, and wherein a source of the NMOS transistor is configured to couple to a ground terminal.

20. The computer program product of claim 11 , wherein the second segment of inductor is coupled to the first segment of inductor using the first capacitor.

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhou Yunfang

Classifications

• H03B5/1228 Primary

  the amplifier comprising one or more field effect transistors · CPC title

• H03B5/08 Primary

  with frequency-determining element comprising lumped inductance and capacitance · CPC title

• H03B5/1212

  the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair · CPC title

• H03B5/1296

  the feedback circuit comprising a transformer · CPC title

• H03B5/1243

  the means comprising voltage variable capacitance diodes · CPC title