Hybrid digital linear and switched capacitor voltage regulator

Patent metadata

Field	Value
Publication number	US-11757357-B2
Application number	US-202217714969-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Sep 6, 2019
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

An on-die voltage regulator (VR) is provided that can deliver much higher conversion efficiency than the traditional solution (e.g., FIVR, LDO) during the standby mode of a system-on-chip (SOC), and it can save the power consumption significantly, during the connected standby mode. The VR operates as a switched capacitor VR under the low load current condition that is common during the standby mode of the SOC, while it automatically switches to the digital linear VR operation to handle a sudden high load current condition at the exit from the standby condition. A digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-averaging (PDA) controller is used to achieve a very low power operation with stability and robustness. As such, the hybrid VR achieves much higher conversion efficiency than the linear voltage regulator (LVR) for low load current condition (e.g., lower than 500 mA).

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of switch capacitor drivers coupled to an input supply node and an output supply node, wherein the output supply node is to provide an output voltage to one or more loads;
a controller coupled to the plurality of switch capacitor drivers and to cause the plurality of switch capacitor drivers to operate in a switch capacitor regulation mode or a linear regulation mode in accordance with a current demand of the one or more loads; and
a comparator coupled to the controller, wherein the comparator is to receive at least three inputs, and wherein the at least three inputs include: a version of an output voltage, the output voltage, and a reference voltage.

2. The apparatus of claim 1 , wherein the controller is to receive one or more outputs of the comparator and to generate a digital code to enable or disable one or more switch capacitor drivers of the plurality of switch capacitor drivers based on the one or more outputs of the comparator.

3. The apparatus of claim 2 , wherein the comparator includes:
a first circuitry to differentiate the output voltage and to generate a first output indicative of the differentiation;
a second circuitry to average the version of the output voltage and to generate a second output indicative of the average; and
a third circuitry to compare the version of the output voltage with the reference voltage, and to generate a third output indicative of the comparison.

4. The apparatus of claim 3 , wherein the comparator is further to generate a fourth output that corresponds to a weighted sum of the first, second, and third outputs.

5. The apparatus of claim 4 , wherein the one or more outputs of the comparator received by the controller include the fourth output.

6. The apparatus of claim 1 , wherein the comparator is a proportional-differential-averaging (PDA) comparator.

7. The apparatus of claim 1 , further comprising a digital-to-analog (DAC) converter to generate the reference voltage in accordance with a bandgap reference and a digital code.

8. The apparatus of claim 1 , wherein an individual switch capacitor driver of the plurality of switch capacitor drivers includes:
at least two capacitors; and
a plurality of transistors some of which are coupled to the at least two capacitors, wherein the plurality of transistors are controllable by two different phases of a clock.

9. The apparatus of claim 1 , wherein an individual switch capacitor driver of the plurality of switch capacitor drivers are operable as a 2:3 divider or a 1:2 divider.

10. The apparatus of claim 1 , wherein the switch capacitor drivers are to operate in the switch capacitor regulation mode if the current demand is less than a threshold, and are to operate in the linear regulation mode if the current demand is greater than the threshold.

11. The apparatus of claim 10 , wherein the threshold is about 100 milli-amperes.

12. A system comprising:
a memory;
a processor core coupled to the memory; and
a voltage regulator coupled to the processor core, wherein the voltage regulator includes:
a plurality of switch capacitor drivers coupled to an input supply node and an output supply node, wherein the output supply node is to provide an output voltage to the processor core;
a controller coupled to the plurality of switch capacitor drivers and to cause the plurality of switch capacitor drivers to operate in a switch capacitor regulation mode or a linear regulation mode in accordance with current demand of the processor core; and
a comparator coupled to the controller, wherein the comparator is to receive at least three inputs, and wherein the at least three inputs include: a version of an output voltage, the output voltage, and a reference voltage.

13. The system of claim 12 , wherein the controller is to receive one or more outputs of the comparator and to generate a digital code to enable or disable one or more switch capacitor drivers of the plurality of switch capacitor drivers based on the one or more outputs of the comparator.

14. The system of claim 12 , wherein the comparator includes:
a first circuitry to differentiate the output voltage and to generate a first output indicative of the differentiation;
a second circuitry to average the version of the output voltage and to generate a second output indicative of the average; and
a third circuitry to compare the version of the output voltage with the reference voltage, and to generate a third output indicative of the comparison.

15. The system of claim 14 , wherein the comparator is further to generate a fourth output that corresponds to a weighted sum of the first, second, and third outputs.

16. The system of claim 15 , wherein one or more outputs of the comparator received by the controller include the fourth output.

17. The system of claim 12 , wherein the comparator is a proportional-differential-averaging (PDA) comparator.

18. The system of claim 12 , wherein an individual switch capacitor driver of the plurality of switch capacitor drivers includes:
at least two capacitors; and
a plurality of transistors some of which are coupled to the at least two capacitors, wherein the plurality of transistors are controllable by two different phases of a clock.

19. The system of claim 12 , wherein the switch capacitor drivers are to operate in the switch capacitor regulation mode if the current demand is less than a threshold, and are to operate in the linear regulation mode if the current demand is greater than the threshold.

20. The system of claim 12 , further comprising a wireless interface to enable the processor core to communicate with another device.

Assignees

• Intel Corp

Inventors

• Oshita Takao
• Paillet Fabrice
• Jain Rinkle
• Rizk Jad
• Bronstein Danny
• Arnaot Ahmad

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H03K5/249

  using clock signals · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title