Galvanic isolation of integrated closed magnetic path transformer with BT laminate

Patent metadata

Field	Value
Publication number	US-11756718-B2
Application number	US-201816236571-A
Country	US
Kind code	B2
Filing date	Dec 30, 2018
Priority date	Dec 30, 2018
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A transformer respectively includes a first isolation barrier, a first inductive element, a second isolation barrier, and a second inductive element. The first isolation barrier and second isolation barrier each comprise multiple isolation layers. The transformer also includes magnetic material including a top magnetic portion disposed above the first isolation barrier. The transformer also includes a bottom magnetic portion disposed below the second inductive element; The transformer further includes an intermediary magnetic portion extending from the top magnetic portion to the bottom magnetic portion via a through-hole within the first isolation barrier, first inductive element, second isolation barrier, and second inductive element. The transformer yet further includes at least one lateral magnetic portion extending from the top magnetic portion to the bottom magnetic portion. The at least one lateral magnetic portion is disposed laterally from the first isolation barrier, first inductive element, second isolation barrier, and second inductive element.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first isolation barrier including first and second isolation layers without a metal layer between the first and second isolation layers, in which the first and second isolation layers each includes a respective pre-preg layer and form a first laminate having a first through-hole, the second isolation layer has opposite first and second sides, and the first side opposes the first isolation layer;
a first metal layer embedded in the second side of the second isolation layer, the first metal layer including a primary coil of a transformer;
a second isolation barrier including third and fourth isolation layers without a metal layer between the third and fourth isolation layers, in which the third and fourth isolation layers each includes a respective pre-preg layer and form a second laminate having a second through-hole, the fourth isolation layer has opposite third and fourth sides, and the third side opposes the third isolation layer;
a second metal layer embedded in the fourth side of the fourth isolation layer, the second metal layer including a secondary coil of the transformer;
magnetic material having a first magnetic portion over at least a portion of the first isolation barrier, a second magnetic portion over all of the second metal layer, and a third magnetic portion between the first and second magnetic portions and extending through the first and second through-holes; and
a lead frame on which the second magnetic portion is mounted, in which the second magnetic portion is between the second metal layer and the lead frame.

2. The integrated circuit of claim 1 , wherein the first and second isolation barriers extend along a first direction; and
wherein the first and second through-holes and the third magnetic portion extend along a second direction normal to the first direction.

3. The integrated circuit of claim 1 , wherein the magnetic material includes a fourth magnetic portion between the first and second magnetic portions and external to the first and second isolation barriers.

4. The integrated circuit of claim 3 , wherein the magnetic material includes a fifth magnetic portion connecting the first and second magnetic portions and external to the first and second isolation barriers; and
wherein the first isolation barrier, the first metal layer, the second isolation barrier, and the second metal layer are between the fourth and fifth magnetic portions.

5. The integrated circuit of claim 1 , wherein at least one of the first through fourth isolation layers includes bismaleimide triazine (BT).

6. The integrated circuit of claim 1 , wherein at least one of the first through fourth isolation layers includes fabric and resin materials.

7. The integrated circuit of claim 6 , wherein the resin materials include bismaleimide triazine (BT).

8. The integrated circuit of claim 1 , further comprising a third metal layer between the first metal layer and the second isolation barrier, and a fourth metal layer between the second metal layer and the second magnetic portion.

9. The integrated circuit of claim 8 , wherein the first and third metal layers include the primary coil.

10. The integrated circuit of claim 8 , wherein the second and fourth metal layers include the secondary coil.

11. The integrated circuit of claim 1 , wherein the first isolation barrier includes a first dielectric layer and the second isolation barrier includes a second dielectric layer,
wherein the first metal layer is embedded in the first dielectric layer; and
wherein the second metal layer is embedded in the second dielectric layer.

12. The integrated circuit of claim 1 , wherein a thickness of the first isolation barrier is between 70 μm and 130 μm.

13. The integrated circuit of claim 1 , wherein a thickness of the second isolation barrier is between 100 μm and 170 μm.

14. The integrated circuit of claim 1 , wherein a thickness of the transformer is between 800 μm and 1200 μm.

15. The integrated circuit of claim 1 , wherein the third magnetic portion includes a beveled portion facing the first magnetic portion, and wherein the transformer includes a filler between the beveled portion and the first magnetic portion.

16. The integrated circuit of claim 15 , wherein the filler comprises epoxy.

17. The integrated circuit of claim 1 , wherein the first magnetic portion has a convex shape.

18. The integrated circuit of claim 1 , wherein the integrated circuit is part of a surface-mounted integrated circuit.

19. The integrated circuit of claim 1 , wherein the integrated circuit is part of a small outline integrated circuit.

20. The integrated circuit of claim 1 , further comprising a first solder mask layer between the first magnetic portion and the first isolation barrier, and a second solder mask layer between the second metal layer and the second magnetic portion.

21. The integrated circuit of claim 1 , wherein the second isolation barrier includes a fifth isolation layer between the third and fourth isolation layers.

22. An integrated circuit comprising:
a first isolation barrier including first and second isolation layers without a metal layer, in which the first and second isolation layers each includes a respective pre-preg layer and form a first laminate having a first through-hole, the second isolation layer has opposite first and second sides, and the first side opposes the first isolation layer;
a first metal layer on or embedded in the second side of the second isolation layer, the first metal layer including a primary coil of a transformer;
a second isolation barrier having opposite third and fourth sides and a second through-hole, in which the third side opposes the first metal layer and the first isolation barrier;
a second metal layer embedded in the fourth side of the second isolation barrier, the second metal layer including a secondary coil of the transformer;
magnetic material having a first magnetic portion over at least a portion of the first isolation barrier, a second magnetic portion over all of the second metal layer, and a third magnetic portion connecting the first and second magnetic portions and extending through the first and second through-holes; and
a lead frame on which the second magnetic portion is mounted, in which the second magnetic portion is between the second metal layer and the lead frame.

23. The integrated circuit of claim 22 , wherein at least one of the first and second isolation layers include bismaleimide triazine (BT).

24. The integrated circuit of claim 22 , further comprising a fourth magnetic portion between the first and second magnetic portions and external to the first and second isolation barriers.

25. The integrated circuit of claim 22 , wherein the second isolation barrier includes third and fourth isolation layers without a metal layer between the third and fourth isolation layers, in which the third and fourth isolation layers each includes a respective pre-preg layer and form a second laminate having the second through-hole.

26. The integrated circuit of claim 25 , wherein the second isolation barrier includes a fifth isolation layer between the third and fourth isolation layers.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Zhemin
• Massolini Roberto Giampiero
• Mullenix Joyce Marie

Classifications

• H10W90/00

  Package configurations · CPC title

• H01F19/08 Primary

  Transformers having magnetic bias, e.g. for handling pulses · CPC title

• H01F2019/085

  Transformer for galvanic isolation · CPC title

• H01F27/2804

  Printed windings · CPC title

• H01F2027/2809

  on stacked layers · CPC title