Computer and calculation method using memristor array

Patent metadata

Field	Value
Publication number	US-11756616-B2
Application number	US-202117522959-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Feb 19, 2021
Publication date	Sep 12, 2023
Grant date	Sep 12, 2023

Abstract

A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.

First claim

What is claimed is:

1. A computer comprising:
a memristor array including memristors, the memristors being arranged at intersections between a plurality of word lines and a first bit line in the memristor array and being arranged at intersections between the plurality of word lines and a plurality of second bit lines in the memristor array;
an adder circuit configured to obtain sum voltages for the plurality of second bit lines by adding a plurality of first voltages to difference voltages, the plurality of first voltages being voltages generated according to currents that flow in the plurality of second bit lines when a first pattern is supplied to the plurality of word lines, the difference voltages being voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the plurality of word lines and a plurality of second voltages generated according to currents that flow in the plurality of second bit lines when a second pattern is supplied to the plurality of word lines; and
a detection circuit configured to detect a second bit line that corresponds to a maximum value of the sum voltages.

2. The computer according to claim 1 , wherein
the memristors arranged at the intersections between the plurality of word lines and the first bit line are set to a low-resistance state,
the memristors arranged at the intersections between the plurality of word lines and the plurality of second bit lines are set to a resistance state that corresponds to a pattern to be compared that is compared with the first pattern, and
the second pattern is an inverted pattern of the first pattern.

3. The computer according to claim 2 , wherein
the first pattern is an input vector, and
the pattern to be compared stored in the memristors connected to the second bit line that corresponds to the maximum value of the sum voltages is a nearest-neighbor vector closest to the input vector.

4. The computer according to claim 1 , the computer comprising:
a plurality of memristor arrays logically two-dimensionally arranged, wherein
the adder circuit obtains the sum voltages for each of columns of the memristor arrays arranged in a first direction, and
the detection circuit includes:
a plurality of first maximum value detection circuits that obtains maximum values of the sum voltages for the respective columns,
a second maximum value detection circuit that obtains a maximum value among the maximum values for the respective columns obtained by the plurality of first maximum value detection circuits, and
an address detection circuit that detects an address that indicates the second bit line that corresponds to the maximum value obtained by the second maximum value detection circuit.

5. The computer according to claim 1 , the computer comprising:
a first holding circuit that holds the plurality of first voltages;
a second holding circuit that holds the reference voltage and the plurality of second voltages;
a difference circuit that obtains difference voltages between the reference voltage held by the second holding circuit and the plurality of second voltages, respectively; and
a third holding circuit that holds the difference voltages,
so as to correspond to the memristor array.

6. The computer according to claim 5 , comprising:
a fourth holding circuit of at least one stage that sequentially holds the plurality of first voltages held by the first holding circuit, wherein
the adder circuit adds the plurality of first voltages held by the fourth holding circuit in a final stage to the plurality of difference voltages.

7. The computer according to claim 1 , comprising:
a current-voltage conversion circuit that converts currents that flow in the first bit line and the plurality of second bit lines into voltages, respectively, according to data stored in each of the memristors when the plurality of word lines is driven; and
a changeover switch that supplies a ground voltage to a ground terminal of the current-voltage conversion circuit when the first pattern is supplied to the plurality of word lines and supplies a bias voltage higher than the ground voltage to the ground terminal of the current-voltage conversion circuit when the second pattern is supplied to the plurality of word lines, wherein
the first pattern and the second pattern are the same as each other.

8. The computer according to claim 1 , the computer comprising:
the current-voltage conversion circuit that converts the currents that flow in the first bit line and the plurality of second bit lines into the voltages, respectively, according to the data stored in each of the memristors when the plurality of word lines is driven;
a selector that connects any one of a plurality of bit line groups that includes a predetermined number of the second bit lines among the plurality of second bit lines to the current-voltage conversion circuit; and
a selection unit that allows the selector to select the second bit line that corresponds to the maximum value of the sum voltages obtained by the detection circuit for each of the bit line groups.

9. A calculation method performed by a computer that includes a memristor array in which memristors are arranged at intersections between a plurality of word lines and a first bit line and at intersections between the plurality of word lines and a plurality of second bit lines, the calculation method comprising:
generating a plurality of first voltages according to currents that flow in the plurality of second bit lines when a first pattern is supplied to the plurality of word lines;
generating a reference voltage according to a current that flows in the first bit line and generating a plurality of second voltages according to currents that flow in the plurality of second bit lines, respectively, when a second pattern is supplied to the plurality of word lines;
obtaining difference voltages between the reference voltage and the plurality of second voltages, respectively;
adding the plurality of first voltages to the plurality of difference voltages, respectively, and obtaining sum voltages for the plurality of second bit lines; and
detecting a second bit line that corresponds to a maximum value of the sum voltages.

Assignees

• Fujitsu Ltd

Inventors

• Nakao Hiroshi
• Hiromoto Masayuki
• Akima Hisanao
• Ishihara Teruo
• Yamamoto Takuji

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C2013/009

  Write using potential difference applied between cell electrodes · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title