High frequency AC coupled self-biased divider

Patent metadata

Field	Value
Publication number	US-11750180-B2
Application number	US-202117469402-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 8, 2021
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

First claim

What is claimed is:

1. A circuit, comprising:
a clock generation circuit configured to generate a differential clocking signal;
a pair of capacitors configured to receive the differential clocking signal; and
a self-biased divider comprising inputs coupled to the pair of capacitors to receive the differential clocking signal, wherein the self-biased divider is configured to output a quadrature clocking signal where at least two clocking signals in the quadrature clocking signal are fed back to perform DC biasing on the differential clocking signal.

2. The circuit of claim 1 , further comprising:
feedback paths coupled to two outputs of the self-biased divider and respective ends of the pair of capacitors.

3. The circuit of claim 2 , wherein the feedback paths comprise respective resistors coupled at one ends to the outputs of the self-biased divider and at second ends to the pair of capacitors.

4. The circuit of claim 3 , wherein first ends of the pair of capacitors are coupled to both the feedback paths and the inputs to self-biased divider and second ends of the pair of capacitors are coupled to the clock generation circuit.

5. The circuit of claim 1 , wherein the two clocking signals have a phase offset of 180 degrees.

6. The circuit of claim 1 , wherein a frequency of the quadrature clocking signal is reduced relative to a frequency of the differential clocking signal by a power of two.

7. The circuit of claim 1 , wherein there are no inverters disposed between the pair of capacitors and the inputs of the self-biased divider.

8. An integrated circuit (IC) comprising:
a clock generation circuit configured to generate an analog clocking signal;
a pair of capacitors configured to receive the analog clocking signal; and
a self-biased divider comprising inputs coupled to the pair of capacitors to receive the analog clocking signal, wherein the self-biased divider is configured to output a quadrature clocking signal where at least two clocking signals in the quadrature clocking signal are fed back to perform DC biasing on the analog clocking signal.

9. The IC of claim 8 , further comprising:
feedback paths coupled to two outputs of the self-biased divider and respective ends of the pair of capacitors.

10. The IC of claim 9 , wherein the feedback paths comprise respective resistors coupled at one ends to the outputs of the self-biased divider and at second ends to the pair of capacitors.

11. The IC of claim 10 , wherein first ends of the pair of capacitors are coupled to both the feedback paths and the inputs to self-biased divider and second ends of the pair of capacitors are coupled to the clock generation circuit.

12. The IC of claim 8 , wherein the two clocking signals have a phase offset of 180 degrees.

13. The IC of claim 8 , wherein a frequency of the quadrature clocking signal is reduced relative to a frequency of the analog clocking signal by a power of two.

14. The IC of claim 8 , wherein there are no inverters disposed between the pair of capacitors and the inputs of the self-biased divider.

15. A method comprising:
AC coupling a differential clocking signal to a pair of capacitors;
receiving the AC coupled clocking signal at a self-biased divider coupled to the pair of capacitors;
outputting a quadrature clocking signal using the self-biased divider; and
feeding back at least two clocking signals in the quadrature clocking signal to perform DC biasing at the pair of capacitors.

16. The method of claim 15 , wherein the two clocking signals are fed back using feedback paths coupled to two outputs of the self-biased divider and respective ends of the pair of capacitors.

17. The method of claim 16 , wherein the feedback paths comprise respective resistors coupled at one ends to outputs of the self-biased divider and at second ends to the pair of capacitors.

18. The method of claim 17 , wherein first ends of the pair of capacitors are coupled to both the feedback paths and the inputs to self-biased divider and second ends of the pair of capacitors are coupled to the clock generation circuit.

19. The method of claim 15 , wherein the two clocking signals have a phase offset of 180 degrees.

20. The method of claim 15 , wherein there are no inverters disposed between the pair of capacitors and inputs of the self-biased divider.

Assignees

• IBM

Inventors

• Strom James
• Kesselring Grant P
• Davies Andrew D
• Wu Ann Chen

Classifications

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• H03B5/12

  active element in amplifier being semiconductor device (H03B5/14 takes precedence) · CPC title

• H03B19/14

  by means of a semiconductor device · CPC title