Switch-mode AC-DC power converter for reducing common mode noise

US11750097B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11750097-B2
Application numberUS-202117453534-A
CountryUS
Kind codeB2
Filing dateNov 4, 2021
Priority dateJan 8, 2020
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A switch-mode AC-DC power converter includes a pair of input terminals, a pair of output terminals, and four switches coupled in a bridgeless totem-pole circuit arrangement between the pair of input terminals and the pair of output terminals. A control circuit is coupled to the four switches and configured to, during a cycle of an AC voltage input, turn on the first switch, turn off the second switch, and apply pulse-width modulation (PWM) control signals to the third and fourth switches. The control circuit is also configured to, during a zero crossing of the AC voltage input, supply a PWM control signal to the fourth switch to reduce a rate of voltage change across the second switch at the zero crossing to reduce common mode noise of the power converter.

First claim

Opening claim text (preview).

The invention claimed is: 1. A switch-mode AC-DC power converter comprising: a bridgeless totem-pole circuit arrangement comprising a first switch, a second switch, a third switch, and a fourth switch; and a control circuit coupled to the bridgeless totem-pole circuit arrangement; wherein the control circuit is configured to: during a cycle of an AC voltage input, turn on the first switch, turn off the second switch, and apply pulse-width modulation (PWM) control signals to the third and fourth switches; prior to a zero crossing of the AC voltage input at an end of the cycle, turn off the first and third switches; and during a zero crossing of the AC voltage input at the end of the cycle, supply a PWM control signal to the fourth switch to reduce a rate of voltage change across the second switch at the zero crossing to reduce common mode noise of the power converter. 2. The power converter of claim 1 further comprising: a pair of input terminals coupled to the bridgeless totem-pole circuit arrangement and configured to receive the AC voltage input; and a pair of output terminals coupled to the bridgeless totem-pole circuit arrangement and configured to supply a DC voltage output to a load. 3. The power converter of claim 2 , wherein: the pair of input terminals comprises a line input terminal and a neutral input terminal; the pair of output terminals comprises a positive output terminal and a negative output terminal; the first switch is coupled between the line input terminal and the positive output terminal; the second switch is coupled between the line input terminal and the negative output terminal; the third switch is coupled between the neutral input terminal and the positive output terminal; and the fourth switch is coupled between the neutral input terminal and the negative output terminal. 4. The power converter of claim 1 , wherein the control circuit is further configured to: stop supplying the PWM control signal to the fourth switch after the zero crossing of the AC voltage input; and turn on the second switch a specified time period after stopping the supply of the PWM control signal to the fourth switch. 5. The power converter of claim 4 , wherein, in response to the AC voltage input changing from a negative polarity to a positive polarity, the control circuit is further configured to turn on the second switch before a drain-to-source voltage (Vds) of the second switch exits a state of clamping to a value of the voltage output at one of the pair of output terminals. 6. The power converter of claim 1 , wherein the cycle of the AC voltage input is a first cycle having a first polarity, and the control circuit is further configured to: during a second cycle of the AC voltage input having a second polarity opposite the first polarity, turn on the second switch, turn off the first switch, and apply PWM control signals to the third and fourth switches; prior to a zero crossing of the AC input voltage at an end of the second cycle, turn off the second switch and the fourth switch; and during the zero crossing of the AC voltage input at the end of the second cycle, supply a PWM control signal to the third switch to reduce a rate of voltage change across the first switch during the zero crossing to reduce the common mode noise of the power converter. 7. The power converter of claim 6 , wherein the control circuit is further configured to: stop supplying the PWM control signal to the third switch after the zero crossing of the AC voltage input; and turn on the first switch a specified time period after stopping the supply of the PWM control signal to the third switch. 8. The power converter of claim 7 , wherein, in response to the AC voltage input changing from a positive polarity to a negative polarity, the control circuit is further configured to, after stopping supply of the PWM control signal to the third switch, turn on the first switch before a Vds of the first switch exits a state of clamping to a value of the voltage output at the other one of the pair of output terminals. 9. The power converter of claim 1 further comprising: a circuit node defined between the third switch and the fourth switch; and an inductor coupled between one of the pair of input terminals and the circuit node. 10. The power converter of claim 1 , wherein the first switch and the second switch comprise metal-oxide semiconductor field-effect transistors (MOSFETs). 11. The power converter of claim 10 , wherein each MOSFET includes a total capacitance across a Vds of the MOSFET, and the control circuit is further configured to supply the PWM control signal to the fourth switch during the zero crossing of the AC voltage input to reduce the rate of voltage change across the second MOSFET by reducing a rate of discharge of the total capacitance across the Vds of the second MOSFET. 12. The power converter of claim 1 further comprising: a circuit node defined between one of the output terminals, the second switch and the fourth switch; an earth ground; and a capacitor coupled between the circuit node and the earth ground. 13. The power converter of claim 1 , wherein the third switch and the fourth switch comprise gallium nitride (GaN) or silicon carbide (SiC) switching devices. 14. The power converter of claim 1 , wherein the PWM control signal comprises a PWM control signal having a fixed on time. 15. The power converter of claim 14 , wherein a frequency of the PWM control signal is greater than a resonance frequency at a node between the first switch and the second switch. 16. A method of controlling a switch-mode AC-DC power converter including a bridgeless totem-pole circuit arrangement between a pair of input terminals and a pair of output terminals, the bridgeless totem-pole circuit arrangement comprising first, second, third, and fourth switches, the method comprising: receiving an AC voltage input having a first polarity at the pair of input terminals; during a first cycle of the AC voltage input, turning on the first switch, turning off the second switch, and applying pulse-width modulation (PWM) control signals to the third and fourth switches; turning off the first and third switches prior to a zero crossing of the AC voltage input at an end of the first cycle; and during a zero crossing of the AC voltage input at the end of the cycle, supplying a PWM control signal to the fourth switch to reduce a rate of voltage change across the second switch at the zero crossing to reduce common mode noise of the power converter. 17. The method of claim 16 further comprising: stopping supply of the PWM control signal to the fourth switch after the zero crossing of the AC voltage input at the end of the first cycle; and turning on the second switch a specified time period after stopping the supply of the PWM control signal to the fourth switch. 18. The method of claim 17 , wherein, in response to the AC voltage input changing from a negative polarity to a positive polarity at the end of the first cycle, turning on the second switch comprises turning on the second switch before a drain-to-source voltage (Vds) of the second switch exits a state of clamping to a value of the voltage output at one of the pair of output terminals. 19. The method of claim 16 further comprising: during a second cycle of the AC voltage input having a second polarity opposite the first polarity, turning on the second switch and turning off the first switch and applying PWM control signals to the third and fourth switches; turning off th

Assignees

Inventors

Classifications

  • H02M3/158Primary

    including plural semiconductor devices as final control devices for a single load · CPC title

  • using passive filters · CPC title

  • in a bridge configuration · CPC title

  • by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title

  • Suppression of common mode voltage or current · CPC title

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What does patent US11750097B2 cover?
A switch-mode AC-DC power converter includes a pair of input terminals, a pair of output terminals, and four switches coupled in a bridgeless totem-pole circuit arrangement between the pair of input terminals and the pair of output terminals. A control circuit is coupled to the four switches and configured to, during a cycle of an AC voltage input, turn on the first switch, turn off the second …
Who is the assignee on this patent?
Astec Int Ltd
What technology area does this patent fall under?
Primary CPC classification H02M3/158. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).