Semiconductor package device

Patent metadata

Field	Value
Publication number	US-11749612-B2
Application number	US-202117536158-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Dec 2, 2020
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.

First claim

What is claimed is:

1. A semiconductor package device, comprising:
a flexible carrier, which includes a flexible layer that has a patterned build-up circuit and is flexible, and a rigid layer combined with a part of a surface of the flexible layer, wherein, the part where the flexible layer is combined with the rigid layer is formed as a first carrying part and a second carrying part, and the flexible layer without the rigid layer between the first carrying part and the second carrying part is formed as a first flexible part;
a first chip, which has an active surface and a non-active surface opposite to each other, and is combined to the first carrying part by flip-chip manner with a side of active surface;
a first molding layer, which is disposed on the first carrying part, and covers the first carrying part and the first chip;
a first adhesive layer, which is disposed on the first molding layer for the second carrying part to be combined with the first molding layer, and the first flexible part connecting the second carrying part and the first carrying part is bent at least 180-degree;
a second chip, which has an active surface and a non-active surface opposite to each other, and is combined to the second carrying part by flip-chip manner with the side of active surface; and
a second molding layer, which is disposed on the second carrying part and covers the second carrying part and the second chip;
wherein the first carrying part and the second carrying part are electrically connected to each other by the patterned build-up circuit in the flexible carrier.

2. The semiconductor package device of claim 1 , wherein a bottom of the first carrying part is electrically connected to a circuit board.

3. The semiconductor package device of claim 1 , further comprising:
a sixth chip, which is embedded in the first molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the first chip by a side of non-active surface through a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying part by a first lead.

4. The semiconductor package device of claim 1 , further comprising:
a third chip, which is embedded in the second molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the second chip by a side of non-active surface through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second carrying part by a second lead.

5. The semiconductor package device of claim 1 , further comprising:
a sixth chip, which is embedded in the first molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the first chip by a side of non-active surface through a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying part by a first lead; and
a third chip, which is embedded in the second molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the second chip by the side of non-active surface through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second carrying part by a second lead.

6. The semiconductor package device of claim 1 , wherein the flexible carrier further includes a second flexible part, which only has the flexible layer, and a third carrying part, which has the flexible layer and the rigid layer, the third carrying part is connected to the second carrying part through the second flexible part, and the third carrying part and the first carrying part are disposed on a same plane, and the semiconductor package device further comprising:
a fourth chip, which has an active surface and a non-active surface opposite to each other, and is combined to the third carrying part with the side of active surface by flip-chip manner; and
a third molding layer, which is disposed on the third carrying part and covers the third carrying part and the fourth chip;
wherein, the first carrying part, the second carrying part, and the third carrying part are electrically connected by the patterned build-up circuit in the flexible carrier.

7. The semiconductor package device of claim 6 , wherein a bottom of the third carrying part is electrically connected to a circuit board.

8. The semiconductor package device of claim 6 , further comprising:
a fifth chip, which is embedded in the third molding layer and has an active surface and a non-active surface opposite to each other, is combined to the non-active surface of the fourth chip through a third adhesive layer with the non-active surface, where the active surface of the fifth chip is electrically connected to the third carrying part by a third lead.

9. The semiconductor package device of claim 6 , further comprising:
a fifth chip, which is embedded in the third molding layer and has an active surface and a non-active surface opposite to each other, is combined to the non-active surface of the fourth chip through a third adhesive layer with the non-active surface, where the active surface of the fifth chip is electrically connected to the third carrying part by a third lead; and
a third chip, which is embedded in the second molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the second chip by the side of non-active surface through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second carrying part by a second lead.

10. The semiconductor package device of claim 6 , further comprising:
a fifth chip, which is embedded in the third molding layer and has an active surface and a non-active surface opposite to each other, is combined to the non-active surface of the fourth chip through a third adhesive layer with the non-active surface, where the active surface of the fifth chip is electrically connected to the third carrying part by a third lead;
a sixth chip, which is embedded in the first molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the first chip by the side of non-active surface through a fourth adhesive layer, wherein the active surface of the sixth chip is electrically connected to the first carrying part by a first lead; and
a third chip, which is embedded in the second molding layer, has an active surface and a non-active surface opposite to each other, and is combined to the non-active surface of the second chip by the side of non-active surface through a second adhesive layer, wherein the active surface of the third chip is electrically connected to the second carrying part by a second lead.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Yu Chun-Hsien
• Hsu Shih-Ping
• Tsai Hsien-Ming

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title