Method of manufacturing semiconductor package

Patent metadata

Field	Value
Publication number	US-11749574-B2
Application number	US-202117388521-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Sep 25, 2014
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Devised are a supporting substrate capable of contributing to an increase in density of a semiconductor package and a laminate using the supporting substrate. A supporting glass substrate of the present invention includes a polished surface on a surface thereof and has a total thickness variation of less than 2.0 μm.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor package, the method comprising the steps of:
preparing a supporting glass substrate free of any through holes, the supporting glass substrate comprising a first surface and a second surface opposite to the first surface and the supporting glass substrate having a Young's modulus of 65 GPa or more;
sandwiching the first surface and the second surface of the supporting glass substrate with a pair of polishing pads;
polishing the first surface and the second surface of the supporting glass substrate, which is free of any through holes, so that the supporting glass substrate has a total thickness variation of less than 5.0 μm while rotating the supporting glass substrate and the pair of polishing pads together so that a part of the supporting glass substrate intermittently extends off from the polishing pads during the polishing;
preparing a processed substrate, the processed substrate comprising at least a semiconductor chip molded with a sealing material;
laminating the polished supporting glass substrate and the processed substrate to obtain a laminate;
conveying the laminate; and
subjecting the processed substrate of the laminate to processing treatment after the conveying.

2. The method of manufacturing a semiconductor package according to claim 1 , wherein the processing treatment comprises a step of arranging wiring on a first surface of the processed substrate.

3. The method of manufacturing a semiconductor package according to claim 2 , wherein the processing treatment further comprises a step of forming a solder bump on the first surface of the processed substrate.

4. The method of manufacturing a semiconductor package according to claim 2 , wherein the supporting glass substrate is formed by an overflow down-draw method.

5. The method of manufacturing a semiconductor package according to claim 2 , wherein the supporting glass substrate has a total thickness variation of less than 2.0 μm.

6. The method of manufacturing a semiconductor package according to claim 2 , wherein the supporting glass substrate has a warpage level of 60 μm or less.

7. The method of manufacturing a semiconductor package according to claim 1 , wherein the processing treatment comprises a step of forming a solder bump on a first surface of the processed substrate.

8. The method of manufacturing a semiconductor package according to claim 1 , wherein the supporting glass substrate is formed by an overflow down-draw method.

9. The method of manufacturing a semiconductor package according to claim 1 , wherein the supporting glass substrate has a total thickness variation of less than 2.0 μm.

10. The method of manufacturing a semiconductor package according to claim 1 , wherein the supporting glass substrate has a warpage level of 60 μm or less.

Assignees

• Nippon Electric Glass Co

Inventors

• Katayama Hiroki

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W74/01

  Manufacture or treatment · CPC title