Method of manufacturing semiconductor devices including the steps of removing a plurality of spacers that surrounds each of the plurality of nanotubes into a layer of nanotubes, and forming gate dielectric and/or gate electrode

Patent metadata

Field	Value
Publication number	US-11749528-B2
Application number	US-202217736505-A
Country	US
Kind code	B2
Filing date	May 4, 2022
Priority date	May 15, 2020
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
aligning a plurality of nanotubes into a layer of nanotubes, each nanotube within the layer of nanotubes being surrounded by a respective one of a plurality of spacers;
removing the spacers; and
forming a gate dielectric over and between the plurality of nanotubes.

2. The method of claim 1 , wherein the spacers comprise a surfactant.

3. The method of claim 2 , wherein the surfactant comprises sodium dodecyl sulfate.

4. The method of claim 1 , wherein the spacers comprise a polymer.

5. The method of claim 4 , wherein the polymer comprises poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-(6,6′ -{2,2′ -bipyridine }) .

6. The method of claim 1 , wherein the spacers comprise 9, 9-dioctylfluorene.

7. The method of claim 1 , wherein the spacers comprise boron nitride nanotubes.

8. A method of manufacturing a semiconductor device, the method comprising:
applying an electromagnetic field to a filter;
reducing a pressure on a first side of the filter, wherein the reducing the pressure and the electromagnetic field cause a plurality of spacers to align adjacent to each other in multiple layers, each spacer surrounding a nanotube;
removing a first one of the multiple layers to form a reduced layer of nanotubes;
removing the spacers from the reduced layer of nanotubes;
depositing a gate dielectric around the nanotubes within the reduced layer of nanotubes; and
depositing a gate electrode over the gate dielectric.

9. The method of claim 8 , wherein the removing the spacers comprises annealing the spacers.

10. The method of claim 8 , wherein the removing the spacers comprises etching the spacers.

11. The method of claim 8 , wherein the applying the electromagnetic field to the filter comprises flowing a surfactant through the filter.

12. The method of claim 8 , wherein the applying the electromagnetic field to the filter comprises coating the filter with a coating material.

13. The method of claim 12 , wherein the coating material comprises poly(vinylpyrrolidone).

14. The method of claim 12 , wherein the coating material comprises aluminum oxide.

15. A method of manufacturing a semiconductor device, the method comprising:
receiving a first nanotube and a second nanotube, wherein a first spacer surrounds the first nanotube and a second spacer surrounds the second nanotube;
depositing the first nanotube adjacent to the second nanotube, wherein after the depositing the first nanotube the first nanotube is parallel with the second nanotube and is spaced apart from the second nanotube by a first distance, the first distance being a sum of a first thickness of the first spacer and a second thickness of the second spacer;
placing the first nanotube and the second nanotube onto a substrate;
removing the first spacer and the second spacer; and
depositing a gate electrode over the first nanotube and the second nanotube.

16. The method of claim 15 , wherein the depositing the first nanotube adjacent to the second nanotube comprises filtering the first nanotube and the second nanotube with a filter.

17. The method of claim 16 , wherein the filter has an electromagnetic field during the depositing the first nanotube adjacent to the second nanotube.

18. The method of claim 15 , wherein after the depositing the first nanotube adjacent to the second nanotube the first nanotube and the second nanotube have a pitch of less than about 100 nm.

19. The method of claim 15 , wherein the placing the first nanotube and the second nanotube is performed at least in part using a transfer layer.

20. The method of claim 19 , wherein the transfer layer comprises polymethyl-methacrylate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chao Tzu-Ang
• Pitner Gregory Michael
• Chen Tse-An
• Li Lain-Jong
• Lin yu chao

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10K71/40

  Thermal treatment, e.g. annealing in the presence of a solvent vapour · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8303

  Diamond · CPC title