Package comprising an ion-trap and method of fabrication

Patent metadata

Field	Value
Publication number	US-11749518-B2
Application number	US-202016913932-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jul 18, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A package-level, integrated high-vacuum ion-chip enclosure having improved thermal characteristics is disclosed. Enclosures in accordance with the present invention include first and second chambers that are located on opposite sides of a chip carrier, where the chambers are fluidically coupled via a conduit through the chip carrier. The ion trap is located in the first chamber and disposed on the chip carrier. A source for generating an atomic flux is located in the second chamber. The separation of the source and ion trap in different chambers affords thermal isolation between them, while the conduit between the chambers enables the ion trap to receive the atomic flux.

First claim

What is claimed is:

1. An ion-trap enclosure comprising:
a chip carrier having a first surface and a second surface that is distal to the first surface;
an ion trap, wherein the ion trap is disposed on a substrate that is disposed on the first surface;
a source that is dimensioned and arranged to provide an atomic flux that predominantly includes neutral atoms of a first material to the ion trap along a first axis;
a first housing, the first housing and the first surface being joined at a first seal such that the first housing and the first surface collectively define a first chamber that contains the ion trap, wherein the first housing includes a first window that enables optical coupling between the ion trap and a first light signal that is directed along a second axis that is substantially orthogonal to the first axis, the first light signal being operative for photo-ionizing at least one neutral atom of the plurality thereof at the ion trap; and
a second housing, the second housing and the second surface being joined at a second seal such that the second housing and the second surface collectively define a second chamber that contains the source;
wherein the first chamber and second chamber are fluidically coupled.

2. The ion-trap enclosure of claim 1 wherein the source includes an oven selected from the group consisting of (i) an ablation oven that generates the atomic flux via laser ablation of the first material and (ii) a thermal oven that provides the atomic flux via sublimation of the first material.

3. The ion-trap enclosure of claim 1 wherein the first light signal is directed along a first direction and the atomic flux propagates along a second direction that is substantially orthogonal with the first direction.

4. The ion-trap enclosure of claim 2 wherein the second housing is configured to enable optical coupling between the first material and a first light signal that is operative for ablating the first material, and wherein the second housing, the source, and the ion trap are arranged such that the first light signal has an optical path that does not pass through the ion trap.

5. The ion-trap enclosure of claim 1 wherein the enclosure enables a pressure level within the first chamber that is less than or equal to 10 −9 Torr.

6. The ion-trap enclosure of claim 1 wherein the chip carrier includes at least one port that enables passage of the atomic flux from the second chamber to the first chamber.

7. The ion-trap enclosure of claim 1 further comprising an ion pump that is fluidically coupled with the first chamber, wherein the second chamber includes a first sub-chamber and a second sub-chamber, and wherein the ion pump is contained in one of the first and second sub-chambers.

8. The ion-trap enclosure of claim 1 further comprising a getter pump that is fluidically coupled with the first chamber.

9. The ion-trap enclosure of claim 1 further comprising a cryosorption pump that is fluidically coupled with the first chamber.

10. An ion-trap enclosure comprising:
a chip carrier having a first major surface and a second major surface that is distal to the first major surface, the chip carrier including a first seal, a second seal, and a first port that extends through the chip carrier;
a substrate comprising an ion trap and a second port that extends through the substrate, wherein the substrate is mounted on the first major surface such that the ion trap is distal to the first major surface; a source that is dimensioned and arranged to provide an atomic flux that predominantly includes neutral atoms of a first material to the ion trap:
a first chamber that contains the ion trap and excludes the source, the first chamber comprising a first housing that is joined with the first major surface at the first seal, wherein the first housing is configured to enable optical coupling between the ion trap and a first light signal that is operative for photo-ionizing at least one neutral atom of the plurality thereof at the ion trap;
a second chamber that contains the source and excludes the ion trap, the second chamber comprising a second housing that is joined with the second major surface at the second seal; and
a conduit that fluidically couples the first chamber and second chamber, wherein the conduit includes the first and second ports;
wherein the ion-trap enclosure enables a pressure level within the first chamber that is less than or equal to 10−9 Torr.

11. The ion-trap enclosure of claim 10 wherein the source includes an oven selected from the group consisting of (i) an ablation oven that generates the atomic flux via laser ablation of the first material and (ii) a thermal oven that provides the atomic flux via sublimation of the first material.

12. The ion-trap enclosure of claim 11 , wherein the second housing is configured to enable optical coupling between the first material and a second light signal that is operative for ablating the first material, and wherein the second housing, the source, and the ion trap are arranged such that the second light signal has an optical path that does not pass through the ion trap.

13. The ion-trap enclosure of claim 10 further comprising an interposer that is located between the substrate and the chip carrier.

14. A method for forming an ion-trap enclosure, the method comprising:
providing a substrate such that it is disposed on a first major surface of a chip carrier that includes a first port that extends through the chip carrier, wherein the substrate comprises an ion trap and a second port that extends through the substrate, and wherein the substrate and chip carrier are arranged such that the first and second ports are fluidically coupled;
providing a source that is configured to provide an atomic flux that predominantly includes neutral atoms of a first material to the ion trap;
joining a first housing and the first major surface at a first seal to define a first chamber that includes the ion trap and excludes the source, wherein the first chamber is fluidically coupled with a conduit that includes the first and second ports, and wherein the first housing is configured to enable optical coupling between the ion trap and a first light signal that is operative for photo-ionizing at least one neutral atom of the plurality thereof at the ion trap; and
joining a second housing and a second major surface of the chip carrier at a second seal to define a second chamber that includes the source and excludes the ion trap, wherein the second chamber is fluidically coupled with the conduit.

15. The method of claim 14 wherein the first and second chambers are defined such that a pressure level within the first chamber is less than or equal to 10 −9 Torr.

16. The method of claim 14 wherein the source is provided such that it includes an oven that is selected from the group consisting of (i) an ablation oven that generates the atomic flux via laser ablation of the first material and (ii) a thermal oven that provides the atomic flux via sublimation of the first material.

17. The method of claim 16 further comprising providing the second housing such that it enables optical coupling between the first material and a second light signal that is operative for ablating the first material, wherein the second housing, the source, and the ion trap are arranged such that the second light signal has an optical path that does not pass through the ion trap.

Assignees

• Univ Duke

Inventors

• Kim Jungsang
• Hudek Kai
• Vrijsen Geert
• Spivey Robert
• Maunz Peter

Classifications

• H01J49/422 Primary

  Two-dimensional RF ion traps (ion guides without mass selection H01J49/062) · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H01J49/16

  using surface ionisation, e.g. field-, thermionic- or photo-emission · CPC title

• H01J49/24

  Vacuum systems, e.g. maintaining desired pressures · CPC title

• H01J49/42

  Stability-of-path spectrometers, e.g. monopole, quadrupole, multipole, farvitrons · CPC title