Semiconductor memory device capable of performing soft-post-package-repair operation

Patent metadata

Field	Value
Publication number	US-11749366-B2
Application number	US-202217578305-A
Country	US
Kind code	B2
Filing date	Jan 18, 2022
Priority date	Jan 18, 2022
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

First claim

The invention claimed is:

1. An apparatus comprising:
a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data:
a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets; and
a second circuit configured to generate the first signal based on the fuse address generated by the first circuit,
wherein the first circuit is configured to change a frequency of updating the fuse address based on a first signal,
wherein the second circuit is configured to bring the first signal into a first state when the fuse address generated by the first circuit is in a first address range,
wherein the second circuit is configured to bring the first signal into a second state when the fuse address generated by the first circuit is in a second address range,
wherein the first circuit is configured to update the fuse address at a first frequency when the first signal is in the first state, and
wherein the first circuit is configured to update the fuse address at a second frequency lower than the first frequency when the first signal is in the second state.

2. The apparatus of claim 1 , wherein the first circuit includes a first oscillator configured to generate a first clock signal of the first frequency and a second oscillator configured to generate a second clock signal of the second frequency.

3. The apparatus of claim 1 ,
wherein the first circuit includes a third oscillator configured to generate a third clock signal,
wherein the third oscillator is configured to set the third clock signal to a third frequency in order to update the fuse address in the first frequency, and
wherein the third oscillator is configured to set the third clock signal to a fourth frequency lower than the third frequency in order to update the fuse address in the second frequency.

4. The apparatus of claim 1 , wherein the second circuit is configured to, when a second signal is in a third state, latch the fuse address supplied from the first circuit when the fuse data output from the fuse array circuit indicates that the fuse set is available.

5. The apparatus of claim 4 , wherein the second circuit is configured to, when the second signal is in a fourth state, output a repair address supplied from outside instead of the fuse data output from the fuse array circuit when the fuse address supplied from the first circuit matches with the fuse address latched in the second circuit.

6. The apparatus of claim 5 , wherein the first and second circuits are configured to be activated responsive to a soft-post-package-repair command.

7. The apparatus of claim 6 , further comprising a third circuit configured to store a plurality of the fuse data transferred from the fuse array circuit,
wherein the third circuit is configured to store the repair address output from the second circuit during a soft-post-package-repair operation.

8. The apparatus of claim 1 , wherein each of the fuse sets includes a plurality of anti-fuse elements.

9. An apparatus comprising:
a fuse array circuit including a plurality of groups assigned to the fuse bank address, each of the groups including a plurality of fuse sets;
a command decoder configured to receive a soft-post-package-repair command and a soft-post-package-repair address including a bank address and a row address; and
a first circuit configured to sequentially select the plurality of fuse sets to read a fuse data stored therein responsive to the soft-post-package-repair command,
wherein the first circuit is configured to sequentially select the plurality of fuse sets in a first frequency when the fuse bank address assigned to the fuse set currently selected does not match with the bank address, and
wherein the first circuit is configured to sequentially select the plurality of fuse sets in a second frequency lower than the first frequency when the fuse bank address assigned to the fuse set currently selected matches with the bank address.

10. The apparatus of claim 9 , further comprising a second circuit including an available resource detector and a register circuit,
wherein the available resource detector is configured to activate a strobe signal when the fuse data output from the fuse array circuit indicates that the fuse set currently selected is available while the fuse bank address assigned to the fuse set currently selected matches with the bank address, and
wherein the register circuit is configured to latch a fuse address of the fuse set currently selected responsive to the strobe signal.

11. The apparatus of claim 10 , wherein the second circuit further includes a multiplexer configured to output the row address instead of the fuse data output from the fuse array circuit when the fuse address of the fuse set currently selected matches with the fuse address latched in the register circuit.

12. The apparatus of claim 11 ,
wherein the first circuit is configured to sequentially select the plurality of fuse sets twice including first and second rounds responsive to the soft-post-package-repair command,
wherein the available resource detector is configured to be activated in the first round, and
wherein the multiplexer is configured to be activated in the second round.

13. The apparatus of claim 12 , further comprising a third circuit configured to store a plurality of the fuse data transferred from the fuse array circuit,
wherein the third circuit is configured to store the row address output from the second circuit during a soft-post-package-repair operation.

14. The apparatus of claim 9 , wherein each of the fuse sets includes a plurality of anti-fuse elements.

15. An apparatus comprising:
a fuse array circuit including a plurality of fuse sets each assigned to a fuse address and configured to store a fuse data; and
a first circuit configured to sequentially update the fuse address to read the fuse data from the plurality of fuse sets,
wherein the first circuit is configured update the fuse address in a first frequency before the fuse address reaches a first value, and update the fuse address in a second frequency lower than the first frequency after the fuse address reaches the first value.

16. The apparatus of claim 15 , wherein the first circuit is configured stop updating the fuse address after the fuse address reaches a second value different from a maximum value.

17. The apparatus of claim 15 , wherein the first circuit is configured to be activated responsive to a soft-post-package-repair command.

Assignees

• Micron Technology Inc

Inventors

• Matsubara Yasushi
• Wilson Alan
• Someya Minoru

Classifications

• G11C29/787 Primary

  using a fuse hierarchy · CPC title

• G11C29/027 Primary

  in fuses · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C8/18 Primary

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C29/1201

  comprising I/O circuitry · CPC title