Level conversion circuit, driving circuit for display panel, and display apparatus

US11749160B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11749160-B2
Application numberUS-202117907754-A
CountryUS
Kind codeB2
Filing dateOct 12, 2021
Priority dateNov 27, 2020
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a level conversion circuit. The level conversion circuit includes at least two level conversion sub-circuits; and each of the level conversion sub-circuits is further connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals, wherein the first power supply signals provided by the first power supply terminals connected to the at least two level conversion sub-circuits are at different levels, and the second power supply signals provided by the second power supply terminals connected to the at least two level conversion sub-circuits are at different levels.

First claim

Opening claim text (preview).

What is claimed is: 1. A level conversion circuit, comprising: at least two level conversion sub-circuits; and at least one first switch sub-circuit; wherein each of the at least one first switch sub-circuit is connected to at least one of a plurality of input control terminals and at least one of the level conversion sub-circuits; and each of the at least one first switch sub-circuit is configured to provide an input control signal provided by each connected input control terminal to the connected level conversion sub-circuit in response to a first switch control signal; and each of the level conversion sub-circuits is further connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals, each of the output signal terminals being further connected to a gate driving circuit; and each of the level conversion sub-circuits is configured to transmit, in response to the received input control signal, a first power supply signal provided by one first power supply terminal or a second power supply signal provided by one second power supply terminal to each connected output signal terminal; wherein the first power supply signals provided by the first power supply terminals connected to the at least two level conversion sub-circuits are at different levels, and the second power supply signals provided by the second power supply terminals connected to the at least two level conversion sub-circuits are at different levels. 2. The level conversion circuit according to claim 1 , wherein each of the at least one first switch sub-circuit comprises a plurality of first switches; wherein a control terminal of each of the first switches is configured to receive the first switch control signal, a first terminal of each of the first switches is connected to one of the plurality of input control terminals, and a second terminal of each of the first switches is connected to one of the level conversion sub-circuits. 3. The level conversion circuit according to claim 2 , wherein a number of the first switches in each of the at least one first switch sub-circuit is the same as a number of the plurality of input control terminals, and the first switches are connected to the input control terminals in one-to-one correspondence. 4. The level conversion circuit according to claim 1 , comprising a plurality of first switch sub-circuits; wherein each of the plurality of first switch sub-circuits is connected to the plurality of input control terminals and one of the level conversion sub-circuits, and each of the level conversion sub-circuits is connected to the plurality of output signal terminals. 5. The level conversion circuit according to claim 1 , wherein each of the level conversion sub-circuits is connected to a plurality of first power supply terminals and one second power supply terminal; and the level conversion circuit further comprises a switch control sub-circuit and at least two second switch sub-circuits, a number of the second switch sub-circuits in the level conversion circuit being the same as a number of the level conversion sub-circuits; wherein the switch control sub-circuit is connected to each of the second switch sub-circuits, and configured to transmit a second switch control signal to each of the second switch sub-circuits; and each of the second switch sub-circuits is further connected to a plurality of first initial power supply terminals and the plurality of first power supply terminals, the plurality of first initial power supply terminals being in one-to-one correspondence with the plurality of first power supply terminals; and each of the second switch sub-circuits is configured to transmit, in response to the second switch control signal, a first initial power supply signal provided by one first initial power supply terminal to one corresponding first power supply terminal, wherein the first initial power supply signals provided by the plurality of first initial power supply terminals are at different levels. 6. The level conversion circuit according to claim 5 , wherein the switch control sub-circuit comprises a temperature detection secondary circuit and a switch control secondary circuit; wherein the temperature detection secondary circuit is connected to the switch control secondary circuit, and configured to transmit an initial control signal to the switch control secondary circuit based on detected temperature; and the switch control secondary circuit is connected to each of the second switch sub-circuits, and configured to transmit a second switch control signal to each of the second switch sub-circuits based on the initial control signal. 7. The level conversion circuit according to claim 6 , wherein the temperature detection secondary circuit comprises a thermistor, a first resistor and a capacitor; and the switch control secondary circuit comprises a current source ; a second resistor and a third resistor; wherein one end of the thermistor and one end of the capacitor are both connected to a first DC power supply terminal, the other end of the thermistor is connected to a first node, and the other end of the capacitor is connected to a second DC power supply terminal; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to the second DC power supply terminal; the current source is connected to the first node and one end of the second resistor, and the other end of the second resistor is connected to a second node; and one end of the third resistor is connected to the second node, the other end of the third resistor is connected to the second DC power supply terminal, and the second node is connected to each of the second switch sub-circuits. 8. The level conversion circuit according to claim 5 , wherein each of the second switch sub-circuits comprises a plurality of second switches; wherein a control terminal of each of the second switches is connected to the switch control sub-circuit, a first terminal of each of the second switches is connected to one first initial power supply terminal, and a second terminal of each of the second switches is connected to one first power supply terminal. 9. The level conversion circuit according to claim 8 , wherein each of the level conversion sub-circuits is connected to two first power supply terminals; and each of the second switch sub-circuits is connected to two first initial power supply terminals and comprises two second switches. 10. The level conversion circuit according to claim 9 , further comprising at least two amplification sub-circuits, a number of the amplification sub-circuits in the level conversion circuit being the same as the number of the level conversion sub-circuits; wherein an input terminal of each of the amplification sub-circuits is connected to one of the two first initial power supply terminals, and an output terminal of each of the amplification sub-circuits is connected to the other of the two first initial power supply terminals; and each of the amplification sub-circuits is configured to amplify a first initial power supply signal provided by one of the first initial power supply terminals and transmits the amplified first initial power supply signal to the other of the first initial power supply terminals. 11. The level conversion circuit according to claim 10 , wherein each of the amplification sub-circuits comprises an amplifier, a fourth resistor and a fifth resistor; wherein a positive input terminal of the amplifier is connected to one of the two first initial power supply terminals, a negative input terminal of the amplifier is connected to

Assignees

Inventors

Classifications

  • G09G3/20Primary

    for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

  • Details of voltage level shifters arranged for use in a driving circuit · CPC title

  • Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

  • Temperature compensation · CPC title

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What does patent US11749160B2 cover?
Provided is a level conversion circuit. The level conversion circuit includes at least two level conversion sub-circuits; and each of the level conversion sub-circuits is further connected to at least one first power supply terminal, at least one second power supply terminal and at least one of a plurality of output signal terminals, wherein the first power supply signals provided by the first …
Who is the assignee on this patent?
Fuzhou Boe Optoelectronics Tech Co Ltd, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/20. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).