Chip-on-film package, display panel, and display device

Patent metadata

Field	Value
Publication number	US-11749146-B2
Application number	US-202117367574-A
Country	US
Kind code	B2
Filing date	Jul 5, 2021
Priority date	Feb 10, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

A chip-on-film package includes a base substrate on which a first pad region, a second pad region, and a third region located between the first pad region and the second pad region are defined, a dummy pad disposed on the first pad region, input pads disposed on the first pad region, output pads disposed on the second region, a first detection line disposed on the base substrate, and a second detection line disposed on the base substrate. The first detection line is connected to a first input pad and a second input pad via the second pad region to form a first loop between the first input pad and the second input pad, and the second detection line is connected to the dummy pad and the first detection line via the third region to form a second loop between the dummy pad and the first input pad.

First claim

What is claimed is:

1. A chip-on-film package comprising:
a base substrate on which a first pad region extends on a first side defining one side of the base substrate, a second pad region extending on a second side defining an opposite side of the base substrate to the one side of the base substrate, a third pad region located between the first pad region and the second pad region, a first region located between the first pad region and the third pad region, and a second region located between the third pad region and the second pad region are defined;
a plurality of first-pads and a first dummy-pad disposed on the first pad region;
a plurality of second-pads and a second dummy-pad disposed on the second pad region;
a plurality of third-pads and a third dummy-pad disposed on the third pad region;
a first detection line disposed on the base substrate, wherein the first detection line includes a first sub-detection line connected between a first first-pad of the first-pads and a first third-pad of the third-pads and a second sub-detection line connected between a second first-pad of the first-pads and a second third-pad of the third-pads, the first sub-detection line being connected to the second sub-detection line in the first pad region to form a first loop between the first third-pad and the second third-pad; and
a second detection line disposed on the base substrate, wherein the second detection line is connected between the third dummy-pad and the first detection line, the second detection line being connected to the first sub-detection line in the first region to form a second loop between the third dummy-pad and the first third-pad.

2. The chip-on-film package of claim 1 , wherein a first second-pad of the second-pads is connected to the first third-pad of the third-pads via the second pad region, the second region, and the third pad region, and a second second-pad of the second-pads is connected to the second third-pad of the third-pads (INTP) via the second pad region, the second region, and the third pad region.

3. The chip-on-film package of claim 1 , wherein a dummy line is disposed on the substrate, the dummy line being connected between the first dummy-pad and the second dummy-pad via the first pad region, the first region, the third pad region, the second region, and the second pad region.

4. The chip-on-film package of claim 3 , wherein the second detection line comprises at least a portion of the dummy line.

5. The chip-on-film package of claim 1 , wherein the second dummy-pad comprises an alignment key for alignment of the second-pads.

6. The chip-on-film package of claim 1 , wherein the first sub-detection line is connected to the second sub-detection line through a short-pad in the first pad region.

7. The chip-on-film package of claim 1 , wherein the second detection line comprises a detection pattern disposed on the first region in a zigzag pattern.

8. The chip-on-film package of claim 1 , further comprising:
an integrated circuit chip connected to the third dummy-pad and the third-pads in the third pad region,
wherein the integrated circuit chip calculates a first resistance value of the first loop and a second resistance value of the second loop and determines whether at least one of the first pad region and the first region is damaged based on the first resistance value and the second resistance value.

9. The chip-on-film package of claim 8 , wherein
the integrated circuit chip determines whether the first pad region and the first region are damaged based on a pad resistance value of the third-pads and the first resistance value,
the integrated circuit chip determines whether the first region is damaged based on the pad resistance value of the third-pads and the second resistance value, and
the integrated circuit chip determines whether the first pad region is damaged based on a difference value between the first resistance value and the second resistance value.

10. A chip-on-film package comprising:
a base substrate on which a first pad region extends on a first side defining one side of the base substrate, a second pad region extending on a second side defining an opposite side of the base substrate to the one side of the base substrate, a third pad region located between the first pad region and the second pad region, a first region located between the first pad region and the third pad region, and a second region located between the third pad region and the second pad region are defined;
a plurality of first-pads and a first dummy-pad disposed on the first pad region;
a plurality of second-pads and a second dummy-pad disposed on the second pad region;
a plurality of third-pads and a third dummy-pad disposed on the third pad region;
a first detection line disposed on the base substrate, wherein the first detection line includes a first sub-detection line connected between a first first-pad of the first-pads and a first third-pad of the third-pads and a second sub-detection line connected between a second first-pad of the first-pads and a second third-pad of the third-pads, the first sub-detection line being connected to the second sub-detection line in the first pad region; and
a second detection line disposed on the base substrate, wherein the second detection line is connected between the third dummy-pad and the first detection line in the first region.

11. The chip-on-film package of claim 10 , wherein a first second-pad of the second-pads is connected to the first third-pad of the third-pads via the second pad region, the second region, and the third pad region, and a second second-pad of the second-pads is connected to the second third-pad of the third-pads via the second pad region, the second region, and the third pad region.

12. The chip-on-film package of claim 10 , wherein a dummy line is disposed on the substrate, the dummy line (being connected between the first dummy-pad and the second dummy-pad via the first pad region, the first region, the third pad region, the second region, and the second pad region.

13. The chip-on-film package of claim 12 , wherein the second detection line comprises at least a portion of the dummy line.

14. The chip-on-film package of claim 10 , wherein the second dummy-pad comprises an alignment key for alignment of the second-pads.

15. The chip-on-film package of claim 10 , wherein the first sub-detection line is connected to the second sub-detection line through a short-pad in the first pad region.

16. The chip-on-film package of claim 10 , further comprising:
an inspection circuit is connected to the third dummy-pad and the third-pads in the third pad region,
wherein the inspection circuit calculates a first resistance value between the first third-pad and the second third-pad and a second resistance value between the third dummy-pad and the first third-pad, and the inspection circuit determines whether at least one of the first pad region and the first region is damaged based on the first resistance value and the second resistance value.

17. The chip-on-film package of claim 16 , wherein
the inspection circuit determines whether the first pad region and the first region are damaged based on a pad resistance value of the third-pads and the first resistance value,
the inspection circuit determines whether the first region is damaged based on the pad resistance value of the third-pads and the second resistance value, and
the inspection circuit determines whether the first pad region is damaged based on a difference value between the first resistance value and the second resistance value.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Hee-Kwon
• Hong Seungkyun

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W70/688

  Flexible insulating substrates · CPC title

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title