Optical fingerprint recognition circuit

Patent metadata

Field	Value
Publication number	US-11749013-B2
Application number	US-202117182540-A
Country	US
Kind code	B2
Filing date	Feb 23, 2021
Priority date	Aug 24, 2018
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

This application provides an optical signal processing circuit and an electronic device, to improve a signal-to-noise ratio of an output signal of a fingerprint sensor, thereby improving a fingerprint recognition rate. The optical signal processing circuit includes a photosensitive device, an amplifier transistor T 1 , a switch transistor T 2 , a switch transistor T 3 , a readout circuit, a control circuit, and a voltage-adjustable power supply. When the optical signal processing circuit is in a compensation reset phase, the voltage of the gate of T 1 exactly reaches a level at which the amplifier transistor T 1 is turned on. Therefore, when an input voltage and a voltage increment are applied to the gate of T 1 , a gate-source voltage Vgs of T 1 increases, and T 1 amplifies an input voltage signal to generate an output signal.

First claim

What is claimed is:

1. An optical signal processing circuit, comprising a photosensitive device, an amplifier transistor, a first switch transistor, a second switch transistor, a readout circuit, a control circuit, and a voltage-adjustable power supply, wherein
the photosensitive device is connected to a gate of the amplifier transistor, the first switch transistor is bridged between the gate and a drain of the amplifier transistor, a source of the amplifier transistor is connected to the voltage-adjustable power supply, the source or the drain of the amplifier transistor is connected to the readout circuit through the second switch transistor, and the control circuit is connected to the first switch transistor, the second switch transistor, and the voltage-adjustable power supply;
the control circuit is configured to control the optical signal processing circuit to be in a first state, a second state after the first state, and a third state after the second state;
when the optical signal processing circuit is in the first state, the control circuit is configured to:
control the first switch transistor to be turned on,
control the second switch transistor to be turned off, and
control the voltage-adjustable power supply to apply a compensation reset voltage to the source of the amplifier transistor so that a gate-source voltage of the amplifier transistor is equal to a threshold voltage of the amplifier transistor;

when the optical signal processing circuit is in the second state,
the photosensitive device is configured to generate an input voltage applied to the gate of the amplifier transistor; and
the control circuit is configured to:
control the first switch transistor to be turned off,
control the voltage-adjustable power supply to be disconnected from the source of the amplifier transistor, and
control the second switch transistor to be turned off; and

when the optical signal processing circuit is in the third state,
the control circuit is configured to:
control the first switch transistor to be turned off, and
control the second switch transistor to be turned on to apply an output signal of the amplifier transistor to the readout circuit, and

the control circuit is further configured to control the voltage-adjustable power supply to apply a read reference voltage to the source of the amplifier transistor, so that the gate-source voltage of the amplifier transistor is a sum of the threshold voltage of the amplifier transistor, the input voltage, and a voltage increment, wherein the voltage increment is an amplitude difference between the compensation reset voltage and the read reference voltage.

2. The circuit according to claim 1 , wherein the amplifier transistor is an N-type transistor, and the gate of the amplifier transistor is connected to an anode of the photosensitive device.

3. The circuit according to claim 2 , wherein
the drain of the amplifier transistor is connected to the readout circuit through the second switch transistor;
the voltage-adjustable power supply comprises a third switch transistor, a fourth switch transistor, a first power supply node of the compensation reset voltage, and a second power supply node of the read reference voltage, wherein the third switch transistor is connected to the first power supply node, the fourth switch transistor is connected to the second power supply node;
in the first state, the control circuit is configured to control the third switch transistor to be turned on and the fourth switch transistor to be turned off to connect the first power supply node to the source of the amplifier transistor;
in the third state, the control circuit is configured to control the third switch transistor to be turned off and the fourth switch transistor to be turned on to connect the second power supply node to the source of the amplifier transistor; and
in the second state, the control circuit is configured to control the third switch transistor to be turned off and the fourth switch transistor to be turned off to disconnect the first power supply node and the second power supply node from the source of the amplifier transistor.

4. The circuit according to claim 3 , wherein
the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all N-type transistors;
the readout circuit comprises an operational amplifier circuit, and a capacitor;
an inverting input terminal of the operational amplifier circuit is connected to the drain of the amplifier transistor through the second switch transistor;
a non-inverting input terminal of the operational amplifier circuit is connected to a node of a reference voltage; and
the capacitor is coupled between the inverting input terminal and an output terminal of the operational amplifier circuit.

5. The circuit according to claim 2 , wherein the compensation reset voltage is −4.5 V, and the read reference voltage is −6 V.

6. The circuit according to claim 1 , wherein the amplifier transistor is a P-type transistor, and the gate of the amplifier transistor is connected to a cathode of the photosensitive device.

7. The circuit according to claim 6 , further comprising a third switch transistor through which the drain of the amplifier transistor is connected to a bias power supply node of a bias voltage, wherein
an anode of the photosensitive device is connected to the bias power supply node;
the voltage-adjustable power supply comprises a fourth switch transistor, the second switch transistor, a first power supply node of the compensation reset voltage, and a second power supply node of the read reference voltage, wherein the fourth switch transistor is connected to the first power supply node, the source of the amplifier transistor is connected to the readout circuit through the second switch transistor;
the readout circuit comprises an operational amplifier circuit, and a non-inverting input terminal of the operational amplifier circuit is connected to the second power supply node;
in the first state, the control circuit is configured to control the fourth switch transistor to be turned on and the second switch transistor to be turned off to connect the first power supply node to the source of the amplifier transistor;
in the third state, the control circuit is configured to control the fourth switch transistor to be turned off and the second switch transistor to be turned on to connect the second power supply node to the source of the amplifier transistor; and
in the second state, the control circuit is configured to control the fourth switch transistor to be turned off and the second switch transistor to be turned off to disconnect the first power supply node and the second power supply node from the source of the amplifier transistor.

8. The circuit according to claim 7 , wherein
the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are all P-type transistors;
the source of the amplifier transistor is connected to the first power supply node of the compensation reset voltage through the fourth switch transistor;
in the first state, the control circuit is configured to control the first and fourth switch transistors to be turned on and the second and third switch transistors to be turned off;
in the second state, the control circuit is configured to control the first through fourth switch transistors to be turned off; and
in the third state, the control circuit is configured to control the first and fourth switch transistors to be turned off and the second and third switch transistors to be turned on.

9. The circuit according to claim 7 , wherein the bias voltage is −6V, the compens

Assignees

• Huawei Tech Co Ltd

Inventors

• Wang Xilin
• Zhang Honghai
• Xia Lilin

Classifications

• G06V40/1318 Primary

  using electro-optical elements or layers, e.g. electroluminescent sensing · CPC title

• H03K17/9627

  Optical touch switches · CPC title