Payment card storing tokenized information

US11748741B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11748741-B2
Application numberUS-202016939514-A
CountryUS
Kind codeB2
Filing dateJul 27, 2020
Priority dateMar 12, 2015
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided are a payment card, system and method for storing and reading tokenized payment account information from a payment card. In an exemplary embodiment, a payment card may include a substrate forming a body of the payment card, and an electronic chip attached to or included in the substrate. According to various exemplary embodiments, the electronic chip may include a storage storing tokenized payment account information corresponding to a payment account linked to the payment card. The electronic chip may be read by a payment terminal and may provide the tokenized payment information to the payment terminal during reading.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing system comprising: a network interface configured to receive, via a computing network, a token validation request from an integrated circuit card comprising a primary account number (PAN) on a face thereof, the token validation request comprising a tokenized PAN corresponding to the PAN on the face of the integrated circuit card, a transaction entry mode value comprising a value indicating that the tokenized PAN was read from a chip of the integrated circuit card via a chip reader, and a chip cryptogram of the chip of the integrated circuit card from which the tokenized PAN was read; and a processor configured to token validation request based on the chip cryptogram of the chip from which the tokenized PAN was read and transaction entry mode value that indicates that the tokenized PAN was read from the chip of the integrated circuit card via the chip reader, wherein the processor is further configured to control the network interface to transmit, via the computing network, an authorization response to a computing system associated with the token validation request in response to the validation, the authorization response authorizing the tokenized PAN for use in a payment transaction. 2. The computing system of claim 1 , wherein the tokenized PAN includes domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions, and the processor is configured to validate the tokenized PAN based on the domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions. 3. The computing system of claim 1 , wherein the transaction entry mode value comprises a Point-of-Sale (POS) entry mode value representing that the tokenized PAN was read by a contact chip reader. 4. The computing system of claim 1 , wherein the processor is further configured to receive a PIN of a user for verifying that the user is a cardholder of the integrated circuit card, and determine to validate the tokenized PAN based on the PIN. 5. The computing system of claim 1 , wherein the network interface is further configured to receive a second token validation request from a second integrated circuit card which comprises a second tokenized PAN and a second transaction entry mode value identifying a domain in which the second tokenized PAN was entered. 6. The computing system of claim 5 , wherein the processor is further configured to decline the second token validation request when the second transaction entry mode value identifies that the domain in which the second tokenized PAN was entered is any of a magnetic stripe mode, an e-commerce mode, and a card not present mode. 7. A method comprising: receiving, via a computing network, a token validation request from an integrated circuit card comprising a primary account number (PAN) on a face thereof, the token validation request comprising a tokenized PAN corresponding to the PAN on the face of the integrated circuit card, a transaction entry mode value comprising a value indicating that the tokenized PAN was read from a chip of the integrated circuit card via a chip reader, and a chip cryptogram of the chip of the integrated circuit card from which the tokenized PAN was read; validating the token validation request based on the chip cryptogram of the chip from which the tokenized PAN was read and transaction entry mode value that indicates that the tokenized PAN was read from the chip of the integrated circuit card via the chip reader; and transmitting, via the computing network, an authorization response to a computing system associated with the token validation request in response to the validation, the authorization response authorizing the tokenized PAN for use in a payment transaction. 8. The method of claim 7 , wherein the tokenized PAN includes domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions, and the validating comprises validating the tokenized PAN based on the domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions. 9. The method of claim 7 , wherein the transaction entry mode value comprises a Point-of-Sale (POS) entry mode value representing that the tokenized PAN was read by a contact chip reader. 10. The method of claim 7 , further comprising receiving a PIN of a user for verifying that the user is a cardholder of the integrated circuit card, and the determining further comprises determining to validate the tokenized PAN based on the PIN. 11. The method of claim 7 , further comprising receiving a second token validation request from a second integrated circuit card which comprises second tokenized PAN and a second transaction entry mode value identifying a domain in which the second tokenized PAN was entered. 12. The method of claim 11 , further comprising determining to decline the second token validation request when the second transaction entry mode value identifies that the domain in which the second tokenized PAN was entered is any of a magnetic stripe mode, an e-commerce mode, and a card not present mode. 13. A non-transitory computer-readable medium comprising instructions which when executed by a processor cause a computer to perform a method comprising: receiving, via a computing network, a token validation request from an integrated circuit card comprising a primary account number (PAN) on a face thereof, the token validation request comprising a tokenized PAN corresponding to the PAN on the face of the integrated circuit card, a transaction entry mode value comprising a value indicating that the tokenized PAN was read from a chip of the integrated circuit card via a chip reader, and a chip cryptogram of the chip of the integrated circuit card from which the tokenized PAN was read; validating the token validation request based on the chip cryptogram of the chip from which the tokenized PAN was read and transaction entry mode value that indicates that the tokenized PAN was read from the chip of the integrated circuit card via the chip reader; and transmitting, via the computing network, an authorization response to a computing system associated with the token validation request in response to the validation, the authorization response authorizing the tokenized PAN for use in a payment transaction. 14. The non-transitory computer-readable medium of claim 13 , wherein the tokenized PAN includes domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions, and the validating comprises validating the tokenized PAN based on the domain restrictions that only permit the tokenized PAN to be used with chip card reading transactions. 15. The non-transitory computer-readable medium of claim 13 , wherein the transaction entry mode value comprises a Point-of-Sale (POS) entry mode value representing that the tokenized PAN was read by a contact chip reader. 16. The non-transitory computer-readable medium of claim 13 , wherein the method further comprises receiving a PIN of a user for verifying that the user is a cardholder of the integrated circuit card, and the validating comprises validating the tokenized PAN based on the PIN. 17. The non-transitory computer-readable medium of claim 13 , further comprising receiving a second token validation request from a second integrated circuit card which comprises second tokenized PAN and a second transaction entry mode value identifying a domain in which the second tokenized PAN was entered. 18. The non-transitory computer-readable medium of claim 17 , further compr

Assignees

Inventors

Classifications

  • G06Q20/341Primary

    Active cards, i.e. cards including their own processing means, e.g. including an IC or chip · CPC title

  • Protecting personal data, e.g. for financial or medical purposes · CPC title

  • by anonymising data, e.g. decorrelating personal data from the owner's identification · CPC title

  • using an alias or single-use codes · CPC title

  • by active credit-cards adapted therefor (G07F7/1008 takes precedence) · CPC title

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What does patent US11748741B2 cover?
Provided are a payment card, system and method for storing and reading tokenized payment account information from a payment card. In an exemplary embodiment, a payment card may include a substrate forming a body of the payment card, and an electronic chip attached to or included in the substrate. According to various exemplary embodiments, the electronic chip may include a storage storing token…
Who is the assignee on this patent?
Mastercard International Inc
What technology area does this patent fall under?
Primary CPC classification G06Q20/341. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).