Integrated circuit chip device

Patent metadata

Field	Value
Publication number	US-11748603-B2
Application number	US-202017134446-A
Country	US
Kind code	B2
Filing date	Dec 27, 2020
Priority date	Dec 27, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

First claim

The invention claimed is:

1. An integrated circuit chip device configured to perform neural network forward computations, wherein the neural network has n layers, the integrated circuit chip device comprising:
a main processing circuit; and
a plurality of basic processing circuits,
wherein:
the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type;
the main processing circuit is configured to:
receive a first operation instruction;
parse the first operation instruction to obtain a first computation instruction included in an i th layer of the forward computations of the first operation instruction and corresponding input data and weight data of the first operation instruction, wherein:
i is an integer greater than or equal to 1 and less than or equal to n, and when i is greater than or equal to 2, the input data is output data of an (i−1) th layer;

determine a first complexity of the first computation instruction according to the input data, the weight data, and the first computation instruction;
determine a first data type corresponding to the first computation instruction according to the first complexity; and
determine whether to start the data type conversion circuit according to the first complexity, wherein:
the first data type is a floating point data type or a fixed point data type;

classify the input data of the first data type and the weight data of the first data type into a broadcasting data block and a distribution data block according to a type of the first computation instruction;
partition the distribution data block to obtain a plurality of basic data blocks;
distribute the plurality of basic data blocks to at least one of the plurality of basic processing circuits; and
broadcast the broadcasting data block to the plurality of basic processing circuits;

at least one of the plurality of basic processing circuits is configured to:
perform computations on the broadcasting data block of the first data type and the basic data blocks of the first data type to obtain computation results; and
transfer the computation results to the main processing circuit; and

the main processing circuit is further configured to:
process the computation results to obtain an instruction result of the first computation instruction so that computations of the first computation instruction of the i th layer are completed.

2. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to compare the first complexity with a preset threshold, wherein:
when the first complexity is greater than the preset threshold, the main processing circuit is configured to determine the first data type as the fixed point type; and
when the first complexity is less than or equal to the preset threshold, the main processing circuit is configured to determine the first data type as the floating point type.

3. The integrated circuit chip device of claim 2 , wherein:
the main processing circuit is configured to:
determine whether the input data and the weight data belong to a second data type, wherein:
when the second data type differs from the first data type, the main processing circuit is configured to:
convert the input data belonging to the second data type and the weight data belonging to the second data type into input data belonging to the first data type and weight data belonging to the first data type using the data type conversion circuit.

4. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the first computation instruction is a convolution computation instruction, determine the input data as convolution input data and the weight data as a convolution kernel;

the first complexity is computed as: the first complexity=α*C1*kH*kW*M*N*W*C2*H, wherein,
α is a convolution coefficient greater than 1;
C1, kH, kW, M are values of four dimensions of the convolution kernel; and
N, W, C2, H are values of four dimensions of the convolution input data;

when the first complexity is greater than a preset threshold, the main processing circuit is configured to:
determine whether the convolution input data and the convolution kernel are floating point data, wherein:
when the convolution input data and the convolution kernel are not floating point data, the main processing circuit is configured to:
convert the convolution input data into floating point data and the convolution kernel into floating point data; and
perform the convolution computation on the convolution input data of the floating point type and the convolution kernel of the floating point type.

5. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the first computation instruction is a matrix-multiply-matrix computation instruction, determine the input data as a first matrix in the matrix-multiply-matrix computation and the weight data as a second matrix in the matrix-multiply-matrix computation;

the first complexity is computed as: the first complexity=β*F*G*E*F1, wherein:
β is a matrix coefficient greater than or equal to 1;
F and G are row and column values of the first matrix; and
E and F1 are row and column values of the second matrix;

when the first complexity is greater than a preset threshold, the main processing circuit is configured to determine whether the first matrix and the second matrix are floating point data, wherein:
when the first matrix and the second matrix are not floating point data, the main processing circuit is configured to:
convert the first matrix into floating point data and the second matrix into floating point data; and
perform the matrix-multiply-matrix computation on the first matrix of the floating point type and the second matrix of the floating point type.

6. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the first computation instruction is a matrix-multiply-vector computation instruction, determine the input data as a first matrix in the matrix-multiply-vector computation and the weight as a vector in the matrix-multiply-vector computation;

the first complexity is computed as: the first complexity=β*F*G*F1, wherein:
β is a matrix coefficient greater than or equal to 1;
F and G are row and column values of the first matrix; and
F1 is a column value of the vector;

when the first complexity is greater than a preset threshold, the main processing circuit is configured to determine whether the first matrix and the vector are floating point data, wherein:
when the first matrix and the vector are not floating point data, the main processing circuit is configured to:
convert the first matrix and the vector into floating point data; and
perform the matrix-multiply-vector computation on the first matrix and the vector of the floating point data type.

7. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the first computation instruction is a multiplication instruction, classify the input data into a distribution data block and the weight data into a broadcasting data block; and
when the first computation instruction is a convolution instruction, classify the input data into a broadcasting data block and the weight data into a distribution data block.

8. The integrated circuit chip device of claim 1 , wherein:
the i th layer further includes at least one of:
a bias operation, a fully connected operation, a GEMM operation, a GEMV operation, or an activation operation.

9. The integrated circuit

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Liu Shaoli
• Song Xinkai
• Wang Bingrui
• Zhang Yao
• Hu Shuai

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title