Integrated circuit chip device

Patent metadata

Field	Value
Publication number	US-11748601-B2
Application number	US-202017134444-A
Country	US
Kind code	B2
Filing date	Dec 27, 2020
Priority date	Dec 27, 2017
Publication date	Sep 5, 2023
Grant date	Sep 5, 2023

Abstract

An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

First claim

The invention claimed is:

1. An integrated circuit chip device for training a neural network having n layers, n being an integer greater than or equal to 2, wherein the integrated circuit chip device comprises:
a main processing circuit; and
a plurality of basic processing circuits;
wherein:
the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type;
the integrated circuit chip device is configured to:
receive a training instruction;
determine input data and weight group data of a first layer according to the training instruction; and
perform a forward computation of an i th layer of the neural network on the input data and the weight group data of the first layer to obtain an i th output result of the forward computation, i being an integer greater than or equal to 1 and smaller than or equal to n;

the main processing circuit is further configured to:
obtain an i th output result gradient according to the i th output result;
obtain an i th backward computation of backward computations of the i th layer according to the training instruction;
obtain an i th backward computation complexity according to the i th output result gradient, input data of the i th layer, weight group data of the i th layer, and the i th backward computation;
determine an i th back data type corresponding to the i th output result gradient, the input data of the i th layer, and the weight group data of the i th layer according to the i th backward computation complexity; and
classify the i th output result gradient, the input data of the i th layer, and the weight group data of the i th layer into a broadcasting data block and a distribution data block according to a type of the i th backward computation;

at least one of the plurality of basic processing circuits is configured to:
perform computations on the broadcasting data block of the i th back data type and received basic data blocks of the i th back data type to obtain computation results; and
transfer the computation results to the main processing circuit;

the main processing circuit is further configured to:
process the computation results to obtain a weight group gradient of the i th layer and an input data gradient of the i th layer; and
update the weight group data of the i th layer according to the weight group gradient of the i th layer, wherein the i th back data type includes a fixed point type or a floating point type;

the integrated circuit device is further configured to:
perform backward computations of an (i−1) th layer using the input data gradient of the i th layer as an (i−1) th output result gradient of the (i−1) th layer to obtain a weight group gradient of the (i−1) th layer; and
update weight group data of a corresponding layer according to the weight group gradient of the (i−1) th layer, wherein the weight group data includes at least two weights; and

the main processing circuit is further configured to:
when the i th backward computation is a multiplication computation, classify both the input data of the i th layer and the weight group data of the i th layer into distribution data blocks, and the i th output result gradient as a broadcasting data block; and
when the i th backward computation is a convolution computation, classify both the input data of the i th layer and the weight group data of the i th layer into broadcasting data blocks, and the i th output result gradient into a distribution data block.

2. The integrated circuit chip device of claim 1 , wherein the main processing circuit is configured to:
compare the i th backward computation complexity with a preset threshold;
determine the i th back data type as the fixed point type when the i th backward computation complexity is greater than the preset threshold; and
determine the i th back data type as the floating point type when the i th backward computation complexity is less than or equal to the preset threshold.

3. The integrated circuit chip device of claim 2 , wherein the main processing circuit is configured to:
determine whether the i th output result gradient, the input data of the i th layer, and the weight group data of the i th layer belong to an (i+1) th back data type; and
convert the i th output result gradient, the input data of the i th layer, and the weight group data of the i th layer belonging to the (i+1) th back data type to an i th output result gradient, input data of the i th layer, and weight group data of the i th layer belonging to the i th back data type, respectively, using the data type conversion circuit when the (i+1) th back data type differs from the i th back data type.

4. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the i th backward computation is a convolution computation, determine convolution input data as the input data of the i th layer and a convolution kernel as the i th output result gradient;

the i th backward computation complexity is computed as: i th backward computation complexity=α*C1*kW*kH*M*N*W*C2*H, wherein:
α is a convolution coefficient greater than 1;
C1, kW, kH, M are values of four dimensions of the convolution kernel; and
N, W, C2, and H are values of four dimensions of the convolution input data;

when the complexity is greater than a preset threshold, the main processing circuit is configured to:
determine the i th back data type as the floating point type; and
determine whether the convolution input data and the convolution kernel are floating point data; wherein:
when the convolution input data and the convolution kernel are not floating point data, the main processing circuit is configured to:
convert the convolution input data into floating point data and the convolution kernel into floating point data; and
perform the convolution computation on the convolution input data of the floating point type and the convolution kernel of the floating point type.

5. The integrated circuit chip device of claim 1 , wherein:
the main processing circuit is configured to:
when the i th backward computation is a matrix-multiply-matrix computation, determine input data as the input data of the i th layer and a weight as the i th output result gradient;

the complexity is computed as complexity=β*F*G*E*F1, wherein:
β is a matrix coefficient greater than or equal to 1;
F and G are row and column values of the input data of the i th layer; and
E and F1 are row and column values of the weight;

when the complexity is greater than a preset threshold, the main processing circuit is configured to:
determine the i th back data type as the floating point type; and
determine whether the input data and the weight of the i th layer are floating point data, wherein:
when the input data and the weight of the i th layer are not floating point data, the main processing circuit is configured to:
convert the input data of the i th layer into floating point data and the weight of the i th layer into floating point data; and
perform the matrix-multiply-matrix computation on the input data of the floating point type and the weight of the i th layer of the floating point type.

6. The integrated circuit chip device of claim 1 , wherein:
the integrated circuit chip device is further configured to:
when the i th backward computation is a matrix-multiply-vector computation, determine input data as the input data of the i th layer and a weight as the i th output result gradient;

the complexity is computed as complexity=β*F*G*F1, wherein:
β is a matrix coefficient greater than or equal to 1;
F and G are row and column values

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Liu Shaoli
• Song Xinkai
• Wang Bingrui
• Zhang Yao
• Hu Shuai

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/09

  Supervised learning · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title