Display assembly and display apparatus

US11747689B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11747689-B2
Application numberUS-202117788395-A
CountryUS
Kind codeB2
Filing dateMay 27, 2021
Priority dateMay 27, 2020
Publication dateSep 5, 2023
Grant dateSep 5, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display assembly, includes: a first substrate and a second substrate that are disposed opposite, a first liquid crystal layer located between the first substrate and the second substrate, a third substrate disposed at a side of the first substrate away from the second substrate, a second liquid crystal layer located between the first substrate and the third substrate, a first pixel circuit layer disposed between the first substrate and the first liquid crystal layer, a second pixel circuit layer disposed between the third substrate and the second liquid crystal layer, a polarizing device disposed on a side of the second pixel circuit layer away from the second liquid crystal layer, and a first metal wire grid polarizing layer disposed between the first substrate and the first pixel circuit layer. The first metal wire grid polarizing layer is electrically insulated from the first pixel circuit layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A display assembly, comprising: a first substrate and a second substrate that are disposed opposite; a first liquid crystal layer located between the first substrate and the second substrate; a third substrate disposed at a side of the first substrate away from the second substrate; a second liquid crystal layer located between the first substrate and the third substrate; a first pixel circuit layer disposed between the first substrate and the first liquid crystal layer; a second pixel circuit layer disposed between the third substrate and the second liquid crystal layer; a polarizing device disposed on a side of the second pixel circuit layer away from the second liquid crystal layer; and a first metal wire grid polarizing layer disposed between the first substrate and the first pixel circuit layer, the first metal wire grid polarizing layer being electrically insulated from the first pixel circuit layer; wherein the first pixel circuit layer includes at least one first signal line; the first metal wire grid polarizing layer includes at least one first discontinuous region each extending in an extending direction of a first signal line, and an orthogonal projection of the first signal line on the first substrate and an orthogonal projection of a first discontinuous region on the first substrate have an overlapping region; borders of the orthogonal projection of the first signal line on the first substrate that extend in the extending direction of the first signal line are within borders of the orthogonal projection of the first discontinuous region on the first substrate that extend in an extending direction of the first discontinuous region; and in a width direction of the first signal line, a gap exists between a border of the orthogonal projection of the first signal line on the first substrate that extends in the extending direction of the first signal line and a border, close to the border of the orthogonal projection of the first signal line, of the orthogonal projection of the first discontinuous region on the first substrate that extends in the extending direction of the first discontinuous region. 2. The display assembly according to claim 1 , further comprising: a first buffer layer disposed between the first metal wire grid polarizing layer and the first pixel circuit layer. 3. The display assembly according to claim 2 , wherein a thickness of the first buffer layer is in a range from 1.27 μm to 7.0 μm. 4. The display assembly according to claim 1 , wherein the at least one first signal line includes a plurality of first signal lines, and the plurality of first signal lines include first gate lines and/or first data lines. 5. The display assembly according to claim 1 , further comprising: a first common electrode layer, wherein the first common electrode layer and the first metal wire grid polarizing layer are arranged in a stack, and a surface of the first common electrode layer is in direct contact with a surface of the first metal wire grid polarizing layer that is adjacent to the surface of the first common electrode layer; or the display assembly further comprises a first buffer layer, the first common electrode layer is disposed on a side of the first buffer layer away from the first metal wire grid polarizing layer and located between the first pixel circuit layer and the first buffer layer. 6. The display assembly according to claim 1 , wherein the first metal wire grid polarizing layer is used as a first common electrode layer. 7. The display assembly according to claim 6 , wherein the first pixel circuit layer includes a plurality of first pixel electrodes distributed in an array; and the first metal wire grid polarizing layer includes: a plurality of first metal bars; and a plurality of first connection portions, wherein two adjacent first metal bars are connected through at least one first connection portion, and orthogonal projections of the plurality of first connection portions on the first substrate are separated from orthogonal projections of the plurality of first pixel electrodes on the first substrate. 8. The display assembly according to claim 1 , wherein the polarizing device is a second metal wire grid polarizing layer, the second metal wire grid polarizing layer is disposed between the third substrate and the second pixel circuit layer, and the second metal wire grid polarizing layer is electrically insulated from the second pixel circuit layer. 9. The display assembly according to claim 8 , further comprising: a second buffer layer disposed between the second metal wire grid polarizing layer and the second pixel circuit layer. 10. The display assembly according to claim 9 , wherein a thickness of the second buffer layer is in a range from 1.27 μm to 7.0 μm. 11. The display assembly according to claim 8 , wherein the second pixel circuit layer includes at least one second signal line; the second metal wire grid polarizing layer includes at least one second discontinuous region each extending in an extending direction of a second signal line, and an orthogonal projection of the second signal line on the third substrate and an orthogonal projection of a second discontinuous region on the third substrate have an overlapping region. 12. The display assembly according to claim 11 , wherein borders of the orthogonal projection of the second signal line on the third substrate that extend in the extending direction of the second signal line are within borders of the orthogonal projection of the second discontinuous region on the third substrate that extend in an extending direction of the second discontinuous region; and in a width direction of the second signal line, a gap exists between a border of the orthogonal projection of the second signal line on the third substrate that extends in the extending direction of the second signal line and a border, close to the border of the orthogonal projection of the second signal line, of the orthogonal projection of the second discontinuous region on the third substrate that extends in the extending direction of the second discontinuous region. 13. The display assembly according to claim 11 , wherein the at least one second signal line includes a plurality of second signal lines, and the plurality of second signal lines include second gate lines and/or second data lines. 14. The display assembly according to claim 8 , further comprising: a second common electrode layer, wherein the second common electrode layer and the second metal wire grid polarizing layer are arranged in a stack, and a surface of the second common electrode layer is in direct contact with a surface of the second metal wire grid polarizing layer that is adjacent to the surface of the second common electrode layer; or the display assembly further comprises a second buffer layer, the second common electrode layer is disposed on a side of the second buffer layer away from the second metal wire grid polarizing layer and located between the second buffer layer and the second pixel circuit layer. 15. The display assembly according to claim 8 , wherein the second metal wire grid polarizing layer is used as a second common electrode layer. 16. The display assembly according to claim 15 , wherein the second pixel circuit layer includes a plurality of second pixel electrodes distributed in an array; and the second metal wire grid polarizing layer includes: a plurality of second metal bars; and a plurality of second connection portions, wherein two adjacent second metal bars are connected through at least one second

Assignees

Inventors

Classifications

  • Wiring, e.g. gate line, drain line · CPC title

  • Wire-grid polarisers · CPC title

  • G02F1/1347Primary

    Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells · CPC title

  • in which all the liquid crystal cells or layers remain transparent, e.g. FLC, ECB, DAP, HAN, TN, STN, SBE-LC cells (G02F1/13475 takes precedence) · CPC title

  • Polarisers · CPC title

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What does patent US11747689B2 cover?
A display assembly, includes: a first substrate and a second substrate that are disposed opposite, a first liquid crystal layer located between the first substrate and the second substrate, a third substrate disposed at a side of the first substrate away from the second substrate, a second liquid crystal layer located between the first substrate and the third substrate, a first pixel circuit la…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136286. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).