Semiconductor chip with stacked conductor lines and air gaps

Patent metadata

Field	Value
Publication number	US-11742289-B2
Application number	US-202117317510-A
Country	US
Kind code	B2
Filing date	May 11, 2021
Priority date	Apr 12, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a first metallization layer on a substrate and a second metallization layer on the first metallization layer;
plural conductor lines in the first metallization layer, each of the conductor lines having an aspect ratio;
a first conductor line in the second metallization layer and a second conductor line in the second metallization layer in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line having an aspect ratio greater than the aspect ratios of the plural conductor lines; and
a dielectric layer having a portion positioned between the first conductor line and the second conductor line, the portion having an air gap.

2. The semiconductor chip of claim 1 , wherein:
each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion; and
a third conductor line of the second metallization layer comprises a first line portion and a second line portion stacked on the first line portion of the third conductor line, the second metallization layer having a conductive via, the first line portion of the third conductor line and the conductive via having a shared contiguous bulk conductor portion and a shared contiguous barrier layer.

3. The semiconductor chip of claim 1 , comprising plural conductive vias in the first metallization layer, each of the plural conductive vias having a first thickness, a third conductor line of the second metallization layer comprising a first line portion and a second line portion stacked on the first line portion of the third conductor line, the second metallization layer having a conductive via connected to the first line portion of the third conductor line, the conductive via having a second thickness greater than the first thickness.

4. The semiconductor chip of claim 1 , wherein the second metallization layer comprises a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, each of the first conductor line and the second conductor line being positioned partially in the first dielectric layer and partially in the second dielectric layer.

5. The semiconductor chip of claim 1 , wherein the plural conductor lines having a first lateral spacing, the first conductor line and the second conductor line of the second metallization layer having a second lateral spacing smaller than the first lateral spacing.

6. The semiconductor chip of claim 1 , comprising a circuit board, the semiconductor chip being mounted on the circuit board.

7. A method of manufacturing a semiconductor chip, comprising:
fabricating a first conductor line in one of a plurality of metallization layers and a second conductor line in the one of the plurality of metallization layers in spaced apart relation to the first conductor line; and
fabricating a dielectric layer having a portion positioned between the first conductor line and the second conductor line, the portion having an air gap.

8. The method of claim 7 , wherein:
the fabricating of the first conductor line and the second conductor line further comprises fabricating each of the first conductor line and the second conductor line to have a first line portion and a second line portion stacked on the first line portion; and
the method further comprises fabricating a third conductor line in the one of the metallization layers with a first line portion and a second line portion stacked on the first line portion of the third conductor line, and fabricating a conductive via in the one of metallization layers, the first line portion of the third conductor line and the conductive via having a shared contiguous bulk conductor portion and a shared contiguous barrier layer.

9. The method of claim 7 , further comprising:
wherein the fabricating of the first conductor line and the second conductor line further comprises fabricating each of the first conductor line and the second conductor line to have a first line portion and a second line portion stacked on the first line portion, wherein the second line portion of the first conductor line has a first thickness and the air gap has a second thickness greater than the first thickness.

10. The method of claim 7 , comprising fabricating plural conductor lines in another of the metallization layers, each of the plural conductor lines having a first thickness, the first conductor line of the one metallization layer having a second thickness greater than the first thickness.

11. The method of claim 7 , comprising fabricating plural conductive vias in another of the metallization layers, each of the plural conductive vias having a first thickness, and fabricating a third conductor line of the one of the metallization layers with a first line portion and a second line portion stacked on the first line portion of the third conductor line, the one of the metallization layers having a conductive via connected to the first line portion of the third conductor line, the conductive via having a second thickness greater than the first thickness.

12. The method of claim 7 , wherein the one of the metallization layers comprises a first dielectric layer and a second dielectric layer stacked on the first dielectric layer, each of the first conductor line and the second conductor line being positioned partially in the first dielectric layer and partially in the second dielectric layer.

13. The method of claim 7 , comprising fabricating plural conductor lines in another of the metallization layers, the plural conductor lines having a first lateral spacing, the first conductor line and the second conductor line of the one metallization layer having a second lateral spacing smaller than the first lateral spacing.

14. The method of claim 7 , comprising mounting the semiconductor chip on a circuit board.

15. A method of manufacturing a semiconductor chip, comprising:
fabricating a first metallization layer on a substrate and a second metallization layer on the first metallization layer;
fabricating plural conductor lines in the first metallization layer, each of the conductor lines having an aspect ratio;
fabricating a first conductor line in the second metallization layer and a second conductor line in the second metallization layer in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line having a first line portion and a second line portion stacked on the first line portion, each of the first conductor line and the second conductor line having an aspect ratio greater than the aspect ratios of the plural conductor lines; and
fabricating a dielectric layer having a portion positioned between the first conductor line and the second conductor line, the portion having an air gap.

16. The method of claim 15 , further comprising:
fabricating a third conductor line of the second metallization layer, the fabricating of the third conductor line of the second metallization layer including fabricating a first line portion and a second line portion stacked on the first line portion of the third conductor line; and
fabricating a conductive via in the second metallization layer having, wherein the first line portion of the third conductor line and the conductive via have a shared contiguous bulk conductor portion and a shared contiguous barrier layer.

17. The method of claim 15 further comprising:
fabricating plural conductive vias in the first metallization layer, each of the plural conductive vias having a first thickness;
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Assignees

• Advanced Micro Devices Inc

Inventors

• Schultz Richard

Classifications

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/071

  of dielectric parts thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title