Voltage-controlled gain-cell magnetic memory

Patent metadata

Field	Value
Publication number	US-11742011-B2
Application number	US-202117399583-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 11, 2021
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

First claim

What is claimed is:

1. A magnetic memory structure, comprising:
a two-terminal memory resistive device with a first terminal connected to a bit line (BL), wherein:
the memory resistive device has a baseline resistance larger than 10 MΩ; and
the memory resistive device is eligible to exhibit a ‘1’ state and a ‘0’ state, and exhibit a resistance change between the ‘1’ state and the ‘0’ state;

a first transistor connected in series between a second terminal of the memory resistive device and a first source line (SL); and
a second transistor having a gate connected to the second terminal of the memory resistive device, a drain connected to a bias voltage power, and a source connected to a second SL, wherein:
when the memory resistive device exhibits the ‘1’ state, a gate voltage at the gate of the second transistor is smaller than a threshold voltage of the second transistor; and
when the memory resistive device exhibits the ‘0’ state, the gate voltage at the gate of the second transistor is larger than the threshold voltage of the second transistor.

2. The magnetic memory structure of claim 1 , the memory resistive device is configured to switch between the ‘1’ state and a ‘0’ state by applying voltage pulses, which have different amplitudes with a same polarity.

3. The magnetic memory structure of claim 1 , wherein corresponding to the ‘0’ state and the ‘1’ state, a current flowing through the second transistor changes between 10 3 times and 10 9 times in amplitude.

4. The magnetic memory structure of claim 1 , wherein the first SL and the second SL are connected to ground.

5. The magnetic memory structure of claim 1 further comprising a resistor, which is connected in series between the drain of the second transistor and the bias voltage power.

6. The magnetic memory structure of claim 1 , wherein each of the first transistor and the second transistor is implemented with one of bulk complementary metal-oxide-semiconductor (CMOS), silicon-on-insulator (SOI) technologies, Fin field-effect transistors (FETs), and negative-capacitance (NC) FETs.

7. The magnetic memory structure of claim 1 , wherein a magnetoresistance (MR) change of the memory resistive device is between 20%-40% between the ‘0’ state and the ‘1’ state.

8. The magnetic memory structure of claim 1 , wherein the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ), and comprises:
a fixed magnetic layer;
a free magnetic layer; and
a resonant tunnel barrier disposed between the fixed magnetic layer and the free magnetic layer, wherein:
when the memory resistive device exhibits the ‘1’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is parallel; and
when the memory resistive device exhibits the ‘0’ state, a magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel.

9. The magnetic memory structure of claim 8 , wherein:
the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer is parallel in response to a first BL voltage applied to the BL;
the magnetization direction of the free magnetic layer relative to a magnetization direction of the fixed magnetic layer is antiparallel in response to a second BL voltage applied to the BL; and
the first BL voltage and the second BL voltage have different amplitudes and a same polarity.

10. The magnetic memory structure of claim 9 , wherein the first BL voltage and the second BL voltage change interlayer exchange coupling (IEC) between the fixed magnetic layer and the free magnetic layer of the REC MTJ above a threshold, at which the magnetization direction of the free magnetic layer is determined by the magnetization direction of the fixed magnetic layer.

11. The magnetic memory structure of claim 8 , wherein the fixed magnetic layer and the free magnetic layer each comprises one of iron (Fe), cobalt (Co), nickel (Ni), lanthanum strontium manganite (LSMO), cobalt iron boron (CoFeB), and cobalt iron (CoFe).

12. The magnetic memory structure of claim 11 , wherein the fixed magnetic layer has a thickness in a range of 5 nm to 100 nm, and the free magnetic layer has a thickness in a range of 1 nm to 3 nm.

13. The magnetic memory structure of claim 8 , wherein the resonant tunnel barrier comprises:
a spacer layer disposed between the fixed magnetic layer and the free magnetic layer;
a first oxide layer disposed between the fixed magnetic layer and the spacer layer; and
a second oxide layer disposed between the spacer layer and the free magnetic layer.

14. The magnetic memory structure of claim 13 , wherein:
the spacer layer comprises one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi); and
the first oxide layer and the second oxide layer each comprise one of magnesium oxide (MgO), magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx), iron oxide (Fe 2 O 3 ), titanium oxide (TiO 2 ), zinc oxide (ZnO), niobium oxide (Nb 2 O 5 ), rhodium oxide (Rh 2 O 3 ), tantalum oxide (Ta 2 O 3 ), vanadium oxide (V 2 O 5 ), aluminum oxide (Al 2 O 3 ), and hafnium oxide (HfO 2 ).

15. The magnetic memory structure of claim 14 , wherein the first oxide layer and the second oxide layer each has a thickness in a range of 0.5 nm to 3 nm, and the spacer layer has a thickness in a range of 0.1 nm to 4 nm.

16. The magnetic memory structure of claim 1 , wherein the memory resistive device is a resonant-exchange-controlled (REC) magnetic tunnel junction (MTJ), and comprises:
a fixed magnetic layer;
a free magnetic layer; and
a resonant tunnel barrier providing a quantum well between the fixed magnetic layer and the free magnetic layer, wherein:
when the memory resistive device exhibits the ‘1’ state, an interlayer exchange coupling (IEC) in the resonant tunnel barrier achieves a first IEC peak;
when the memory resistive device exhibits the ‘0’ state, the IEC in the resonant tunnel barrier achieves a second IEC peak; and
the first IEC peak and the second IEC peak have different polarities.

17. The magnetic memory structure of claim 16 , wherein:
the first IEC peak is achieved in response to a first BL voltage applied to the BL;
the second IEC peak is achieved in response to a second BL voltage applied to the BL; and
the first BL voltage and the second BL voltage have different amplitudes and a same polarity.

18. The magnetic memory structure of claim 16 , wherein the resonant tunnel barrier comprises:
a spacer layer disposed between the fixed magnetic layer and the free magnetic layer;
a first oxide layer disposed between the fixed magnetic layer and the spacer layer; and
a second oxide layer disposed between the spacer layer and the free magnetic layer.

19. The magnetic memory structure of claim 18 , wherein:
the spacer layer comprises one of ruthenium (Ru), gold (Au), iridium (Ir), rhodium (Rh), copper (Cu), chromium (Cr), palladium (Pd), molybdenum (Mo), vanadium (V), tantalum (Ta), tungsten (W), platinum (Pt), nickel oxide (NiO), and iron silicon (FeSi); and
the first oxide layer and the second oxide layer each comprise one of magnesium oxide (MgO), magnesium zinc oxide (MgZnO), aluminum monoxide (AlOx), iron oxide (Fe 2 O 3 ), titanium oxide (TiO 2 ), zinc oxide (ZnO), niobium oxide (Nb 2 O 5

Assignees

• Univ California

Inventors

• Salahuddin Sayeef
• Sayed Shehrin

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/80

  Constructional details · CPC title