Technologies for secure hardware and software attestation for trusted I/O

Patent metadata

Field	Value
Publication number	US-11741230-B2
Application number	US-202117451922-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Jul 20, 2015
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

Technologies for trusted I/O attestation and verification include a computing device with a cryptographic engine and one or more I/O controllers. The computing device collects hardware attestation information associated with statically attached hardware I/O components that are associated with a trusted I/O usage protected by the cryptographic engine. The computing device verifies the hardware attestation information and securely enumerates one or more dynamically attached hardware components in response to verification. The computing device collects software attestation information for trusted software components loaded during secure enumeration. The computing device verifies the software attestation information. The computing device may collect firmware attestation information for firmware loaded in the I/O controllers and verify the firmware attestation information. The computing device may collect application attestation information for a trusted application that uses the trusted I/O usage and verify the application attestation information. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. An apparatus, comprising:
a cryptographic engine to secure one or more direct memory access (DMA) channels;
a secure, non-volatile memory to store persistently a first platform device identifier associated with the apparatus; and
a security subsystem, comprising a secure processing element to:
collect attestation information of one or more hardware or software components of the apparatus;
send the attestation information to a remote verification service;
securely enumerate one or more dynamically attached hardware I/O components;
load a secure bus enumerator for the one or more dynamically attached hardware I/O components; and
initialize one or more protected direct memory access (DMA) channels associated with a trusted I/O usage of the security subsystem and protected by the cryptographic engine.

2. The apparatus of claim 1 , the secure processing element to:
discover one or more statically attached hardware I/O components.

3. The apparatus of claim 2 , the secure processing element to:
generate one or more secure enclave reports, wherein each secure enclave report is indicative of a cryptographic measurement of a trusted software component.

4. The apparatus of claim 1 , the secure processing element to:
determine one or more hardware I/O devices of the I/O components;
determine, based on the attestation information, that the one or more hardware I/O devices required is reachable via a secure I/O path from a trusted application associated with the I/O components; and
verify an identity of a trusted software component associated with each secure I/O path.

5. The apparatus of claim 1 , the secure processing element to:
verify at least a portion of the attestation information by a trusted application executing on an apparatus.

6. The apparatus of claim 1 , further comprising a firmware attestation module, executed by the secure processing element, to (i) collect firmware attestation information associated with one or more I/O controllers, and (ii) verify the firmware attestation information.

7. The apparatus of claim 1 , further comprising an application attestation module, executed by the secure processing element, to (i) collect application attestation information associated with a trusted application, wherein the trusted application uses the trusted I/O usage, and (ii) verify the application attestation information.

8. A processor-implemented method, comprising:
securing, in a cryptographic engine, one or more direct memory access (DMA) channels;
storing, in a secure, non-volatile memory, a first platform device identifier associated with an apparatus; and
in a security subsystem comprising a secure processing element:
collecting attestation information of one or more hardware or software components of the apparatus;
sending the attestation information to a remote verification service;
securely enumerating one or more dynamically attached hardware I/O components;
loading a secure bus enumerator for the one or more dynamically attached hardware I/O components; and
initializing one or more protected direct memory access (DMA) channels associated with a trusted I/O usage of the security subsystem and protected by the cryptographic engine.

9. The method of claim 8 , further comprising:
discovering one or more statically attached hardware I/O components.

10. The method of claim 9 , further comprising:
generating one or more secure enclave reports, wherein each secure enclave report is indicative of a cryptographic measurement of a trusted software component.

11. The method of claim 8 , further comprising:
determining one or more hardware I/O devices of the I/O components;
determining, based on the attestation information, that the one or more hardware I/O devices required is reachable via a secure I/O path from a trusted application associated with the I/O components; and
verifying an identity of a trusted software component associated with each secure I/O path.

12. The method of claim 8 , further comprising:
verifying at least a portion of the attestation information by a trusted application executing on an apparatus.

13. The method of claim 8 , further comprising:
collecting firmware attestation information associated with one or more I/O controllers; and
verifying the firmware attestation information.

14. The method of claim 8 , further comprising:
collecting application attestation information associated with a trusted application, wherein the trusted application uses the trusted I/O usage; and
verifying the application attestation information.

15. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations, comprising:
securing, in a cryptographic engine, one or more direct memory access (DMA) channels;
storing, in a secure, non-volatile memory, a first platform device identifier associated with an apparatus; and
in a security subsystem comprising a secure processing element:
collecting attestation information of one or more hardware or software components of the apparatus;
sending the attestation information to a remote verification service;
securely enumerating one or more dynamically attached hardware I/O components;
loading a secure bus enumerator for the one or more dynamically attached hardware I/O components; and
initializing one or more protected direct memory access (DMA) channels associated with a trusted I/O usage of the security subsystem and protected by the cryptographic engine.

16. The computer-readable medium of claim 15 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations, comprising:
discovering one or more statically attached hardware I/O components.

17. The computer-readable medium of claim 16 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations, comprising:
generating one or more secure enclave reports, wherein each secure enclave report is indicative of a cryptographic measurement of a trusted software component.

18. The computer-readable medium of claim 15 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations, comprising:
determining one or more hardware I/O devices of the I/O components;
determining, based on the attestation information, that the one or more hardware I/O devices required is reachable via a secure I/O path from a trusted application associated with the I/O components; and
verifying an identity of a trusted software component associated with each secure I/O path.

19. The computer-readable medium of claim 15 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations, comprising:
verifying at least a portion of the attestation information by a trusted application executing on an apparatus.

20. The computer-readable medium of claim 15 , comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations, comprising:
collecting firmware attestation information associated with one or more I/O controllers; and
verifying the firmware attes

Assignees

• Intel Corp

Inventors

• Pappachan Pradeep M
• Lal Reshma
• Xing Bin
• Chhabra Siddhartha
• Scarlata Vincent R
• Mcgowan Steven B

Classifications

• G06F21/57 Primary

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title