Memory device and operating method of the memory device and host device

Patent metadata

Field	Value
Publication number	US-11740966-B2
Application number	US-202117539898-A
Country	US
Kind code	B2
Filing date	Dec 1, 2021
Priority date	Apr 19, 2021
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A memory device, and an operating method of the memory device and a host device are provided. The method of operating a memory device includes receiving a command for requesting an Eye Open Monitor (EOM) operation performance from a host device, receiving pattern data including data and non-data from the host device, performing the EOM operation which performs an error count to correspond to the data, and does not perform the error count on the non-data, and transmitting an EOM response signal including the error count result to the host device.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
receiving, from a host device, a command requesting an Eye Open Monitor (EOM) operation;
receiving pattern data including one or more data symbols and one or more non-data symbols from the host device, wherein the one or more data symbols includes an information symbol and/or a pattern symbol;
counting, in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols;
not counting, in the error count, second errors corresponding to the one or more non-data symbols; and
transmitting, to the host device, an EOM response signal including the error count.

2. The method of claim 1 , wherein the one or more non-data symbols include
a first non-data symbol, and the first non-data symbol is a filler symbol.

3. The method of claim 2 , further comprising:
determining whether the first non-data symbol is a K28.1 symbol; and
not counting the second errors in response to the first non-data symbol being the K28.1 symbol.

4. The method of operating the memory device of claim 2 , further comprising:
determining whether the first non-data symbol is a D07.3 symbol; and
not counting the second errors in response to the first non-data symbol being the D07.3 symbol.

5. The method of operating the memory device of claim 2 , wherein each of the one or more data symbols and each of the one or more non-data symbols correspond to an N-bit signal, wherein N is a positive integer,
the method further comprising:
decoding the received pattern data into an M-bit signal and a distinction signal, wherein the received pattern data includes a first information symbol and a first control symbol, and M is a positive integer and M is less than N;
descrambling the M-bit signal; and
not counting the second errors in response to the descrambled M-bit signal being the filler symbol.

6. The method of operating the memory device of claim 1 , wherein the one or more non-data symbols includes a second non-data symbol, and the second non-data symbol is a control symbol.

7. The method of operating the memory device of claim 6 , wherein each of the one or more data symbols and each of the one or more non-data symbols corresponds to an N-bit signal, and N is a positive integer,
the method further comprising:
decoding the received pattern data into an M-bit signal and a distinction signal, wherein the received pattern data includes a first information symbol and a first control symbol, M is a positive integer and M is less than N; and
not counting, based on the distinction signal, the second errors.

8. A method of operating a host device, the method comprising:
transmitting, to a memory device, a command requesting an Eye Open Monitor (EOM) operation;
transmitting pattern data including one or more data symbols and one or more non-data symbols to the memory device; and
receiving, from the memory device, an EOM response signal including an error count associated with the pattern data,
wherein the error count is based on the one or more data symbols and is not based on the non-data symbols.

9. The method of operating the host device of claim 8 , wherein the one or more non-data symbols includes a first non-data symbol, and the first non-data symbol is a filler symbol.

10. The method of operating the host device of claim 8 , wherein the one or more non-data symbols includes a second non-data symbol, and the second non-data symbol is a control symbol.

11. A memory device comprising:
an interfacing device; and
a device controller configured to control an operation of the interfacing device,
wherein the interfacing device is configured to:
receive a command requesting an Eye Open Monitor (EOM) operation,
receive, from a host device, pattern data including one or more data symbols and one or more non-data symbols, wherein the one or more data symbols includes an information symbol and/or a pattern symbol,
perform an EOM operation including:
counting, in an error count and as part of the EOM operation, first errors corresponding to the one or more data symbols, and
not counting, in the error count, second errors corresponding to the one or more non-data symbols, and

transmit, to the host device, an EOM response signal including the error count.

12. The memory device of claim 11 , wherein the pattern data is a serial signal and the interfacing device comprises:
an equalizer configured to receive the serial signal and output a serial bit;
a first deserializer configured to, using the serial bit, generate an N-bit main path signal, wherein N is a positive integer;
a second deserializer configured to, using the serial bit, generate an N-bit EOM path signal;
a comparator configured to perform the counting the first errors based on a difference between a main path signal and the N-bit EOM path signal; and
a non-data symbol detector configured to stop a counting performance of the comparator in response to the main path signal including the one or more non-data symbols.

13. The memory device of claim 12 , wherein the non-data symbol detector is configured to stop the counting performance of the comparator, when the N-bit main path signal is either 0011111000 or 1100000110.

14. The memory device of claim 12 , wherein the non-data symbol detector is configured to stop the counting performance of the comparator, when the N-bit main path signal is either 1110001100 or 0001110011.

15. The memory device of claim 11 , wherein the pattern data is a serial signal and the interfacing device comprises:
an equalizer configured to receive the serial signal and output a serial bit;
a first deserializer configured to, using the serial bit, generate an N-bit main path signal, wherein N is a positive integer;
a second deserializer configured to, using the serial bit, generate an N-bit EOM path signal;
a comparator configured to perform the counting the first errors based on a difference between a main path signal and the N-bit EOM path signal; and
a decoder configured to decode the N-bit main path signal into an M-bit signal and a distinction signal, wherein M is a positive integer, and
wherein the comparator is further configured to receive the distinction signal and stop, in response to the distinction signal, a counting by the comparator.

16. The memory device of claim 15 , wherein a value of N is 10 and a value of M is 8.

17. The memory device of claim 11 , wherein the pattern data is a serial signal and the interfacing device comprises:
an equalizer configured to receive the serial signal and output a serial bit;
a first deserializer configured to, using the serial bit, generate an N-bit main path signal, wherein N is a positive integer;
a second deserializer configured to, using the serial bit, generate an N-bit EOM path signal;
a comparator configured to perform the counting the first errors based on a difference between a main path signal and the N-bit EOM path signal;
a decoder configured to decode the N-bit main path signal into an M-bit signal and a distinction signal, wherein M is a positive integer and M is less than N;
a descrambler configured to descramble the M-bit signal; and
a symbol remover configured to remove a filler symbol from the descrambled M-bit signal, and
wherein the comparator is further configured to receive the distinction signal and stop, in response to the distinction signal, a counting by the comparator.

18. The memory device of claim 11 , wherein the pattern data includes a P-bit signal and P i

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Young San
• Jun Walter
• Cho Ye Jin
• Hong Sung Tack

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• H03M13/1108

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title