Vector friendly instruction format and execution thereof

Patent metadata

Field	Value
Publication number	US-11740904-B2
Application number	US-202117524624-A
Country	US
Kind code	B2
Filing date	Nov 11, 2021
Priority date	Apr 1, 2011
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

First claim

What is claimed is:

1. An apparatus comprising:
a processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, and the beta field on each occurrence of an instruction in the first instruction format, the processor including,
a decode unit to decode a plurality of instructions in the first instruction format, wherein the decode unit is configured to decode the plurality of instructions in the first instruction format as follows:
distinguish those of the plurality of instructions that specify memory access from those that do not based on the modifier field's content in those different instructions, wherein part of the beta field is interpreted as an RL field when the modifier field's content does not specify memory access;
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that instruction, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as a vector length field when the RL field's content indicates the vector length type operation;
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the remainder of the beta field's content and its interpretation as the round operation field in that instruction; and
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the vector length type operation through the RL field's content, which one of a plurality of vector lengths to use based on the remainder of the beta field's content and its interpretation as the vector length field in that instruction.

2. The apparatus of claim 1 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero.

3. The apparatus of claim 1 , wherein the plurality of vector lengths includes 128 bits, 256 bits, and 512 bits.

4. The apparatus of claim 1 , wherein, for each of the instructions that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, all floating point exceptions are suppressed.

5. The apparatus of claim 1 , wherein the first instruction format further includes a data element width field, and the contents of two or more of the data element width field, the base operation field, and the vector length field determine a memory access size, the memory access size being used to specify memory access.

6. The apparatus of claim 1 , wherein at least certain of the different version of the base operations operate on two source operands and a destination operand does not overwrite either of the two source operands.

7. The apparatus of claim 1 , wherein at least certain of the different versions of the base operations operate on two source operands and a destination operand overwrites one of the two source operands.

8. The apparatus of claim 1 , wherein the first instruction format further includes a data element width field, wherein the first instruction format supports through different values in the data element width field the specification of different data element widths.

9. The apparatus of claim 8 , wherein the different data element widths include 32 bits and 64 bits.

10. The apparatus of claim 8 , wherein the first instruction format also supports through different values in a real opcode field inside the base operation field the specification of an 8 bit and a 16 bit data element width.

11. The apparatus of claim 8 , wherein the first instruction format further includes a real opcode field inside the base operation field, wherein the real opcode field's content distinguishes whether the data element width field's content selects between a 64 bit and a 32 bit data element size or selects between a 16 bit and an 8 bit data element size for each of the occurrences.

12. A processor configured to execute an instruction set, wherein the instruction set includes a first instruction format, wherein the first instruction format has a plurality of fields including a base operation field, a modifier field, and a beta field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, and the beta field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, and the beta field on each occurrence of an instruction in the first instruction format, the processor comprising:
a decode unit to decode a plurality of instructions in the first instruction format, wherein the decode unit is configured to decode the plurality of instructions in the first instruction format as follows:
distinguish those of the plurality of instructions that specify memory access from those that do not based on the modifier field's content in those different instructions, wherein part of the beta field is interpreted as an RL field when the modifier field's content does not specify memory access;
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content, whether to augment with a round type operation or with a vector length type operation based on the RL field's content in that instruction, wherein a remainder of the beta field is interpreted as a round operation field when the RL field's content indicates the round type operation, and wherein the remainder of the beta field is instead interpreted as a vector length field when the RL field's content indicates the vector length type operation;
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the round type operation through the RL field's content, which one of a plurality of round operations to apply based on the remainder of the beta field's content and its interpretation as the round operation field in that instruction; and
distinguish, for each of the plurality of instructions that does not specify memory access through the modifier field's content and that does specify the vector length type operation through the RL field's content, which one of a plurality of vector lengths to use based on the remainder of the beta field's content and its interpretation as the vector length field in that instruction.

13. The processor of claim 12 , wherein the plurality of round operations includes round to nearest, round down, round up, and round toward zero.

14. The processor of claim 12 , wherein the plurality of vector lengths includes 128 bits, 256 bits, and 512 b

Assignees

• Intel Corp

Inventors

• Valentine Robert C
• San Adrian Jesus Corbal
• Sans Roger Espasa
• Cavin Robert D
• Toll Bret L
• Duran Santiago Galan
• Wiedemeier Jeffrey G
• Samudrala Sridhar
• Girkar Milind Baburao
• Grochowski Edward Thomas
• Hall Jonathan Cannon
• Bradford Dennis R
• Ould-Ahmed-Vall Elmoustapha
• Abel James C
• Charney Mark
• Abraham Seth
• Sair Suleyman
• Forsyth Andrew Thomas
• Wu Lisa
• Yount Charles

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D48/30

  Devices controlled by electric currents or voltages · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title