Circuit and method for combining SPAD outputs

Patent metadata

Field	Value
Publication number	US-11740334-B2
Application number	US-202016898600-A
Country	US
Kind code	B2
Filing date	Jun 11, 2020
Priority date	Jun 18, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.

First claim

The invention claimed is:

1. A combining network for an array of single-photon avalanche diode (SPAD) devices, comprising:
a plurality of synchronous sampling circuits, each synchronous sampling circuit being directly electrically connected to an output of a corresponding SPAD device and being configured to cause a logic high transition of its output at each rising edge of a clock signal where an output of the corresponding SPAD device is at a logic high at the rising edge as a result of a detection event but maintain its output at a logic low at each rising edge of the clock signal where the output of the corresponding SPAD device is not at a logic high at the rising edge as a result of a lack of a detection event;
a summation circuit directly electrically connected to an output of each of the synchronous sampling circuits and configured to count a number of logic high transitions at each rising edge of the clock signal to generate a binary output value representing the number of logic high transitions at that rising edge of the clock signal;
a multi-bit output flip-flop directly electrically connected to an output of the summation circuit to receive the binary output value; and
a histogram generation circuit directly electrically connected to an output of the multi-bit output flip-flop to receive the binary output value.

2. The combining network of claim 1 , wherein the summation circuit comprises an adder tree configured to convert an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log 2 N+1.

3. The combining network of claim 1 , wherein each of the plurality of synchronous sampling circuits comprises a flip-flop having a data input directly electrically connected to the output of the corresponding SPAD device, the flip-flops being clocked by the clock signal.

4. The combining network of claim 3 , wherein the detection event is a pulse of a first duration on the output of the corresponding SPAD device, and the clock signal has a period of less than half the first duration.

5. A ranging device, comprising:
an array of SPAD devices;
a combining network comprising:
a plurality of synchronous sampling circuits, each synchronous sampling circuit being coupled to an output of a corresponding SPAD device from the array of SPAD devices and being configured to cause a logic high transition of its output at each rising edge of a clock signal where an output of the corresponding SPAD device is at a logic high at the rising edge as a result of a detection event but maintain its output at a logic low at each rising edge of the clock signal where the output of the corresponding SPAD device is not at a logic high at the rising edge as a result of a lack of a detection event; and
a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of logic high transitions at each rising edge of the clock signal to generate a binary output value representing the number of logic high transitions at that clock pulse; and

a histogram generation circuit configured to accumulate the binary output values generated by the summation circuits in a plurality of time bins.

6. The ranging device of claim 5 , wherein the summation circuit comprises an adder tree configured to convert an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log 2 N+1.

7. The ranging device of claim 5 , wherein each of the plurality of synchronous sampling circuits comprises a flip-flop having a data input coupled to the output of the corresponding SPAD device, the flip-flops being clocked by the clock signal.

8. The ranging device of claim 7 , wherein the detection event is a pulse of a first duration on the output of the corresponding SPAD device, and the clock signal has a period of less than half the first duration.

9. The ranging device of claim 5 , wherein each of the plurality of synchronous sampling circuits comprises an edge detection device configured to detect an edge of a pulse generated by the corresponding SPAD device.

10. The ranging device of claim 9 , wherein each edge detection device comprises:
a first flip-flop having a data input coupled to the output of the corresponding SPAD device;
a second flip-flop having a data input coupled to a data output of the first flip-flop, wherein the first and second flip-flops are clocked by the clock signal; and
a logic gate coupled to data outputs of the first and second flip-flops and configured to detect an edge at the output of the corresponding SPAD device based on data outputs of the first and second flip-flops.

11. A method of detecting events in a single-photon avalanche diode (SPAD) array, the method comprising:
causing, by a plurality of synchronous sampling circuits, a logic high transition at each rising edge of a clock signal where an output of a corresponding SPAD device of the SPAD array is at a logic high at the rising edge of the clock signal but maintain the output at a logic low where the output of the corresponding SPAD device is not at a logic high at the rising edge of the clock signal;
counting, by a summation circuit coupled to an output of each of the synchronous sampling circuits, a number of logic high transitions at each rising edge of the clock signal to generate a binary output value representing the number of logic high transitions at that rising edge of the clock signal; and
generating a histogram from the binary output values.

12. The method of claim 11 , further comprising converting, using an adder tree of the summation circuit, an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log 2 N+1.

13. The method of claim 11 , wherein causing the logic high transition each time an event is detected at the output of the corresponding SPAD device comprises sampling, using a flip-flop, the output of the corresponding SPAD device based on the clock signal.

Assignees

• St Microelectronics Res & Dev Ltd

Inventors

• Patanwala Sarrah Moiz
• Rae Bruce
• Dutton Neale

Classifications

• G01S7/4863 Primary

  Detector arrays, e.g. charge-transfer gates · CPC title

• G01S7/4865

  Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak (peak detection in noise, signal conditioning G01S7/487) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• G01S17/89

  for mapping or imaging · CPC title

• G01S7/4914

  of detector arrays, e.g. charge-transfer gates · CPC title