Electronic test equipment apparatus and methods of operating thereof

Patent metadata

Field	Value
Publication number	US-11740278-B2
Application number	US-201916529940-A
Country	US
Kind code	B2
Filing date	Aug 2, 2019
Priority date	Aug 2, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.

First claim

What is claimed is:

1. An electronic test equipment apparatus, comprising:
a power terminal configured to receive power;
an interface for a device under test (DUT);
at least one power transistor connected in series between the power terminal and the interface for the DUT; and
a protection circuit configured to:
switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and
subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine.

2. The electronic test equipment apparatus of claim 1 , wherein the protection circuit comprises:
a gate driver circuit configured to drive a gate terminal of the at least one power transistor; and
a controller configured to:
provide a first logic signal to the gate driver circuit for switching on the at least one power transistor, so that the at least one power transistor electrically connects the power terminal to the DUT through the interface as part of the test routine; and
subsequently provide a second logic signal to the gate driver circuit for switching off the at least one power transistor after the predetermined delay, so that the at least one power transistor electrically disconnects the power terminal from the DUT regardless of whether the DUT passes or fails the test routine.

3. The electronic test equipment apparatus of claim 2 , wherein a signal which controls when the DUT turns on as part of the test routine is a trigger input to the controller, and wherein the controller comprises a counter or timer circuit programmed to the predetermined delay and responsive to the trigger input.

4. The electronic test equipment apparatus of claim 1 , wherein the predetermined delay is programmable so that the electronic test equipment apparatus is compatible with different types of DUTs.

5. The electronic test equipment apparatus of claim 1 , wherein the at least one power transistor is a silicon carbide (SiC) power transistor.

6. The electronic test equipment apparatus of claim 1 , wherein the at least one power transistor is an insulated gate bipolar transistor (IGBT).

7. The electronic test equipment apparatus of claim 1 , wherein the interface for the DUT comprises a plurality of probes configured to make electrical contact with the DUT.

8. The electronic test equipment apparatus of claim 7 , wherein the DUT is part of a semiconductor wafer having a plurality of devices, and wherein the electronic test equipment apparatus is a prober interface board configured to probe the semiconductor wafer via the plurality of probes.

9. The electronic test equipment apparatus of claim 7 , further comprising a current limiter circuit configured to limit a current permitted to flow through the plurality of probes.

10. The electronic test equipment apparatus of claim 9 , wherein the current limiter circuit comprises a separate IGBT electrically connected to each individual probe of the plurality of probes, each separate IGBT configured to limit the current permitted to flow through the probe electrically connected to the IGBT by operating in desaturation.

11. The electronic test equipment apparatus of claim 1 , further comprising a voltage clamp circuit configured to limit a voltage applied to the at least one power transistor from the power terminal.

12. The electronic test equipment apparatus of claim 11 , wherein the power terminal is configured to be supplied by an inductive energy source, and wherein the voltage clamp circuit forms part of a current commutation path with the inductive energy source when the at least one power transistor is off.

13. The electronic test equipment apparatus of claim 11 , wherein the voltage clamp circuit comprises one or more clamping diodes connected in series.

14. The electronic test equipment apparatus of claim 11 , wherein the voltage clamp circuit comprises:
a plurality of power MOSFETs connected in series with different voltage tap points, each power MOSFET of the plurality of power MOSFETs being avalanche-rated and capable of handling energy commutated through a current commutation path when the at least one power transistor is switched off; and
a circuit configured to control which power MOSFETs of the plurality of power MOSFETs are on and which power MOSFET of the plurality of power MOSFETs are off, to provide discrete adjustments to the limit of the voltage applied to the at least one power transistor by the voltage clamp circuit.

15. The electronic test equipment apparatus of claim 11 , wherein the voltage clamp circuit comprises:
a plurality of branches of series-connected linear power MOSFETs, each linear power MOSFET of the plurality of linear power MOSFETs having a linear relationship between gate voltage and drain-source on resistance; and
a circuit configured to control which linear power MOSFETs of the plurality of linear power MOSFETs are on and which linear power MOSFET of the plurality of linear power MOSFETs are off, to provide continuous adjustments to the limit of the voltage applied to the at least one power transistor by the voltage clamp circuit.

16. A voltage clamp circuit for electronic test equipment, the voltage clamp circuit comprising:
a plurality of branches of series-connected linear power MOSFETs, each linear power MOSFET of the plurality of linear power MOSFETs having a linear relationship between gate voltage and drain-source on resistance; and
a circuit configured to control which linear power MOSFETs of the plurality of linear power MOSFETs are on and which linear power MOSFET of the plurality of linear power MOSFETs are off, to provide continuous adjustments to a voltage limited by the voltage clamp circuit.

17. A method of testing a device under test (DUT), the method comprising:
probing the DUT via a DUT interface, the DUT interface being electrically connectable to an energy source through at least one power transistor connected in series between the energy source and the DUT interface;
switching on the at least one power transistor, to electrically connect the energy source to the DUT through the DUT interface as part of a test routine; and
subsequently automatically switching off the at least one power transistor after a predetermined delay, to electrically disconnect the energy source from the DUT regardless of whether the DUT passes or fails the test routine.

18. The method of claim 17 , further comprising:
limiting a current permitted to flow to the DUT through a plurality of probes of the DUT interface, by operating a separate IGBT electrically connected to each individual probe of the plurality of probes in desaturation.

19. The method of claim 17 , further comprising:
limiting a voltage applied to the at least one power transistor from the energy source, by controlling a plurality of avalanche-rated power MOSFETs connected in series with different voltage tap points, by controlling which power MOSFETs of the plurality of power MOSFETs are on and which power MOSFET of the plurality of power MOSFETs are off, thereby providing discrete adjustments to a limit of the voltage applied to the at least one power transistor.

20. The method of claim 17 , further comprising:
limiting the voltage applied to the at least one power transistor from the energy source, by controlling a plurality of branches of series-connected linear power MOSFETs having a lin

Assignees

• Infineon Technologies Ag

Inventors

• Roche Kevin
• Diy Alfonso
• Eni Emanuel-Petre
• Niedermeyr Josef
• Tarlac Efren

Classifications

• G01R31/2639 Primary

  for testing field-effect devices, e.g. of MOS-capacitors (G01R31/2621 takes precedence) · CPC title

• G01R1/36

  Overload-protection arrangements or circuits for electric measuring instruments · CPC title

• G01R31/2893

  Handling, conveying or loading, e.g. belts, boats, vacuum fingers (G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H10P72/00) · CPC title

• G01R31/31912

  Tester/user interface · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title