Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate

Patent metadata

Field	Value
Publication number	US-11737266-B2
Application number	US-202117339880-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Mar 1, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a substrate of semiconductor material that includes a first area, a second area and a third area;
recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;
forming a first conductive layer disposed over and insulated from the upper surfaces in the first and second and third areas;
forming an insulation layer on the first conductive layer in the first and second and third areas;
thinning the insulation layer in the third area without thinning the insulation layer in the first and second areas;
forming trenches through the insulation layer and the first conductive layer, and into the substrate, in the first, second and third areas;
filling the trenches with insulation material;
after the filling of the trenches, removing the insulation layer from the first, second and third areas;
forming a second conductive layer disposed over and insulated from the first conductive layer in the first and second and third areas;
performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, to entirely remove the first and second conductive layers from the second and third areas, wherein the one or more etches result in pairs of stack structures in the first area with each of the stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer;
forming first source regions in the substrate each disposed between one of the pairs of stack structures;
forming a third conductive layer disposed over and insulated from the upper surfaces of the substrate in the first and second and third areas;
forming a protective insulation layer over the third conductive layer in the first and second areas;
after the forming of the protective insulation layer, removing the third conductive layer from the third area;
after the removing of the third conductive layer from the third area, forming blocks of dummy conductive material disposed over and insulated from the upper surface in the third area;
after the forming of the blocks of dummy conductive material in the third area, etching portions of the protective insulation layer and portions of the third conductive layer in the first and second areas to form a plurality of select gates of the third conductive layer each disposed adjacent to one of the stack structures and to form a plurality of HV gates of the third conductive layer each disposed over and insulated from the upper surface of the substrate in the second area;
forming first drain regions in the substrate each adjacent to one of the select gates;
forming second source regions in the substrate each adjacent one of the HV gates;
forming second drain regions in the substrate each adjacent one of the HV gates;
forming third source regions in the substrate each adjacent one of the blocks of dummy conductive material;
forming third drain regions in the substrate each adjacent one of the blocks of dummy conductive material; and
replacing each of the blocks of dummy conductive material with a block of metal material.

2. The method of claim 1 , wherein each of the blocks of metal material is insulated from the upper surface of the substrate in the third area by a layer of high K insulation material.

3. The method of claim 1 , wherein before the replacing, each of the blocks of dummy conductive material is insulated from the upper surface of the substrate in the third area by a layer of high K insulation material, and wherein the replacing further comprises forming each of the blocks of metal material on the layer of high K insulation material.

4. The method of claim 1 , wherein for each of the pairs of stack structures, an erase gate of the third conductive layer is disposed between the pair of stack structures, and over and insulated from one of the source regions.

5. The method of claim 1 , wherein each of the first, second and third conductive layers is formed of polysilicon or amorphous silicon.

6. The method of claim 1 , further comprising:
forming silicide on the first, second and third drain regions and on the second and third source regions.

7. The method of claim 4 , further comprising:
before the replacing, forming silicide on the select gates, the erase gates and the HV gates.

8. The method of claim 1 , wherein for each of the stack structures, the control gate is insulated from the floating gate by an ONO insulation layer.

9. The method of claim 4 , wherein the forming of the blocks of dummy conductive material includes forming a logic insulation layer on the blocks of dummy conductive material and a hard mask layer on the logic insulation layer.

10. The method of claim 9 , wherein before the replacing, further comprising:
forming a layer of flowable material in the first, second and third areas;
removing a portion of the layer of flowable material to expose the hard mask layer;
removing the hard mask layer; and
removing the layer of flowable material.

11. The method of claim 10 , further comprising:
forming silicide on the select gates, the erase gates and the HV gates, wherein the logic insulation layer prevents the formation of silicide on the blocks of dummy conductive material.

12. A method of forming a semiconductor device, comprising:
providing a substrate of semiconductor material that includes a first area, a second area and a third area;
recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the second area relative to an upper surface of the substrate in the third area;
forming an insulation layer over the substrate;
thinning the insulation layer in the third area without thinning the insulation layer in the first and second areas;
forming trenches through the insulation layer and into the substrate, in the first, second and third areas;
filling the trenches with insulation material;
after the filling of the trenches, removing the insulation layer from the first and second areas;
forming a first conductive layer disposed over and insulated from the upper surfaces in the first and second;
forming a second conductive layer disposed over and insulated from the first conductive layer in the first and second areas;
performing one or more etches to selectively remove portions of the first and second conductive layers in the first area, and to entirely remove the first and second conductive layers from the second area, wherein the one or more etches result in pairs of stack structures in the first area with each of the stack structures including a control gate of the second conductive layer disposed over and insulated from a floating gate of the first conductive layer;
forming first source regions in the substrate each disposed between one of the pairs of stack structures;
forming a third conductive layer disposed over and insulated from the upper surfaces of the substrate in the first and second areas;
forming a protective insulation layer over the third conductive layer in the first and second areas;
after the forming of the protective insulation layer, removing the protective insulation layer from the third area;
after the removing of the protective insulation layer from the third area, forming blocks of dummy conductive material disposed over and insulated from the upper surface in the third area;
after the forming of the blocks of dummy conductive material in the third area, etching portions of the protective insulation layer and p

Assignees

• Silicon Storage Tech Inc

Inventors

• Song guo xiang
• Wang Chunming
• Xing leo
• Liu Xian
• Do Nhan

Classifications

• H10D84/8314

  the IGFETs characterised by having gate insulating layers with different properties · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title