Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-11735654-B2
Application number	US-202117510913-A
Country	US
Kind code	B2
Filing date	Oct 26, 2021
Priority date	Aug 31, 2017
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

First claim

What is claimed is:

1. A manufacturing method of a silicon carbide semiconductor device including an inverted semiconductor element, the manufacturing method comprising:
preparing a substrate made of silicon carbide of a first or second conductivity type;
forming a drift layer made of silicon carbide of the first conductivity type and having an impurity concentration lower than an impurity concentration of the substrate above the substrate;
forming a base region made of silicon carbide of the second conductivity type above the drift layer;
forming a source region made of silicon carbide of the first conductivity type and having an impurity concentration higher than the impurity concentration of the drift layer above the base region;
forming a trench gate structure by providing, from a surface of the source region, a plurality of gate trenches deeper than the base region and aligned in stripes with one direction as a longitudinal direction, forming a gate insulating film on inner wall surfaces of the gate trenches, and forming a gate electrode on the gate insulating film;
forming a source electrode electrically connected to the source region;
forming a drain electrode to a rear surface of the substrate; and
forming a non-doped layer made of silicon carbide between the forming the base region and the forming the source region,
wherein
the forming the base region and the forming the source region are performed by epitaxial growth, and
the forming the source region includes forming a first source region of the first conductivity type above the base region by epitaxial growth, and forming a second source region of the first conductivity type above the first source region by epitaxial growth, the second source region having an impurity concentration higher than an impurity concentration of the first source region and brought into contact with the source electrode.

2. The manufacturing method according to claim 1 ,
wherein
the forming the base region, the forming the non-doped layer, and the forming the source region are sequentially performed by epitaxial growth, and
the forming the non-doped layer includes performing epitaxial growth in a state of stopping introduction of a first conductivity type dopant gas and a second conductivity type dopant gas to form the non-doped layer with a thickness of 0.05 to 0.2 μm.

3. The manufacturing method according to claim 2 , further comprising
forming a coupling layer of the second conductivity type, which reaches the base region and couples the base region with the source electrode, by ion implantation of a second conductivity type impurity from the surface of the source region after the forming the non-doped layer and the forming the source region, wherein
when a portion of the coupling layer in which the second conductivity type impurity is ion-implanted into the first source region is defined as a first region, and a portion of the coupling layer in which the second conductivity type impurity is ion-implanted into the second source region is defined as a second region, the forming the coupling layer includes forming the second region by ion-implanting the second conductivity type impurity at a dose amount of 2 to 10 times the first conductivity type impurity concentration of the second source region, and then performing an activation by a thermal treatment of 1500° C. or more.

Assignees

• Denso Corp

Inventors

• KAJI Aiko
• Takeuchi Yuichi
• Mitani Shuhei
• Suzuki Ryota
• Yamashita Yusuke

Classifications

• H10P30/2042

  into crystalline silicon carbide · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D62/145

  Emitter regions of IGBTs · CPC title