Metal-oxide-semiconductor field-effect-transistors (MOSFET) as antifuse elements

Patent metadata

Field	Value
Publication number	US-11735521-B2
Application number	US-202117510190-A
Country	US
Kind code	B2
Filing date	Oct 25, 2021
Priority date	Apr 2, 2018
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Embodiments herein may describe techniques for an integrated circuit including a MOSFET having a source area, a channel area, a gate electrode, and a drain area. The channel area may include a first channel region with a dopant of a first concentration next to the source area, and a second channel region with the dopant of a second concentration higher than the first concentration next to the drain area. A source electrode may be in contact with the source area, a gate oxide layer above the channel area, and the gate electrode above the gate oxide layer. A first resistance exists between the source electrode and the gate electrode. A second resistance exists between the source electrode, the gate electrode, and a path through the gate oxide layer to couple the source electrode and the gate electrode after a programming operation is performed. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a source electrode on a source area above a substrate;
a drain electrode on a drain area above the substrate;
a channel area including a first channel region adjacent to the source area, and a second channel region adjacent to the drain area, wherein the first channel region includes a dopant of a first concentration, and the second channel region includes the dopant of a second concentration higher than the first concentration;
a gate oxide layer above the channel area;
a gate electrode above the gate oxide layer; and
a conductive path through the gate oxide layer, the conductive path coupling the source electrode and the gate electrode.

2. The integrated circuit of claim 1 , wherein the substrate is a bulk substrate.

3. The integrated circuit of claim 1 , wherein the substrate is a silicon-on-insulator (SOI) substrate.

4. The integrated circuit of claim 1 , wherein the integrated circuit is a PMOS MOSFET.

5. The integrated circuit of claim 1 , wherein the integrated circuit is an NMOS MOSFET.

6. The integrated circuit of claim 1 , wherein the first concentration of the dopant is in a range of about 10 15 cm −3 to about 10 16 cm −3 , and the second concentration of the dopant is in a range of 10 17 cm −3 to about 10 18 cm −3 .

7. The integrated circuit of claim 1 , wherein the dopant includes Silicon (Si), Germanium (Ge), Carbon (C), or Boron (B).

8. The integrated circuit of claim 1 , wherein the dopant is distributed in a graded pattern.

9. The integrated circuit of claim 1 , wherein the dopant is uniformly distributed in the second channel region.

10. The integrated circuit of claim 1 , wherein the source electrode, the drain electrode, or the gate electrode includes polycrystalline silicon (poly-Si), polycrystalline silicon-germanium, germanium (Ge), cobalt (Co), titanium (Ti), tungsten (W), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), or an alloy of Ti, W, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

11. The integrated circuit of claim 1 , further comprising:
a first selector coupled to the drain electrode; and
a second selector coupled to the source electrode.

12. The integrated circuit of claim 11 , wherein the first selector or the second selector is a PMOS transistor.

13. The integrated circuit of claim 11 , wherein the first selector or the second selector is an NMOS transistor.

14. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a source electrode on a source area above a substrate;
a drain electrode on a drain area above the substrate;
a channel area including a first channel region adjacent to the source area, and a second channel region adjacent to the drain area, wherein the first channel region includes a dopant of a first concentration, and the second channel region includes the dopant of a second concentration higher than the first concentration;
a gate oxide layer above the channel area;
a gate electrode above the gate oxide layer; and
a conductive path through the gate oxide layer, the conductive path coupling the source electrode and the gate electrode.

15. The computing device of claim 14 , further comprising:
a memory coupled to the board.

16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.

17. The computing device of claim 14 , further comprising:
a display coupled to the board.

18. The computing device of claim 14 , further comprising:
a GPS coupled to the board.

19. The computing device of claim 14 , further comprising:
a battery coupled to the board.

20. The computing device of claim 14 , further comprising:
a camera coupled to the board.

Assignees

• Intel Corp

Inventors

• Chao Yu-Lin
• Kulkarni Sarvesh H
• Dorgan Vincent E
• Bhattacharya Uddalak

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H10B20/25

  One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links · CPC title