Semiconductor package device

Patent metadata

Field	Value
Publication number	US-11735491-B2
Application number	US-202117505953-A
Country	US
Kind code	B2
Filing date	Oct 20, 2021
Priority date	Mar 18, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor package device includes a package substrate, an interposer on the package substrate, a semiconductor package on the interposer, and an under-fill between the interposer and the semiconductor package. The interposer includes at least one first trench at an upper portion of the interposer that extends in a first direction parallel to a top surface of the package substrate. The at least one first trench vertically overlaps an edge region of the semiconductor package. The under-fill fills at least a portion of the at least one trench.

First claim

What is claimed is:

1. A semiconductor package device, comprising:
a package substrate;
an interposer on the package substrate;
a semiconductor package on the interposer; and
an under-fill between the interposer and the semiconductor package,
wherein the interposer is provided with at least one first trench at an upper portion of the interposer, the at least one first trench extending in a first direction parallel to a top surface of the package substrate,
wherein the at least one first trench vertically overlaps an edge region of the semiconductor package, and
wherein the under-fill fills at least a portion of the at least one first trench.

2. The semiconductor package device of claim 1 ,
wherein the interposer includes:
a silicon substrate;
a wiring layer on the silicon substrate; and
a pad on the wiring layer,

wherein the wiring layer includes a dielectric layer and a wiring structure in the dielectric layer,
wherein the wiring structure includes a via part in contact with the pad, and
wherein a depth of the first trench is less than a thickness of the via part.

3. The semiconductor package device of claim 2 ,
wherein the dielectric layer includes an epoxy compound and fiberglass impregnated in the epoxy compound.

4. The semiconductor package device of claim 2 ,
wherein the wiring structure further includes a line part connected to the via part, and
wherein the line part is disposed lower than a bottom surface of the first trench.

5. The semiconductor package device of claim 1 ,
wherein the at least one first trench includes a plurality of trenches,
wherein each of the plurality of trenches has a width in a second direction that intersects the first direction, the second direction being parallel to the top surface of the package substrate, and
wherein the plurality of trenches are spaced apart from each other at a pitch in the second direction.

6. The semiconductor package device of claim 5 , wherein
the width has a value between about 10 μm and about 15 μm, and
the pitch has a value between about 10 μm and about 15 μm.

7. The semiconductor package device of claim 5 ,
wherein a depth of each of the plurality of trenches has a value between about 30 μm and about 50 μm.

8. The semiconductor package device of claim 1 ,
wherein the semiconductor package includes:
a first semiconductor chip; and
a plurality of second semiconductor chips stacked on the first semiconductor chip,

wherein the first semiconductor chip includes:
a first semiconductor substrate; and
a plurality of first through electrodes that penetrate the first semiconductor substrate, and

wherein each of the second semiconductor chips includes:
a second semiconductor substrate; and
a plurality of second through electrodes that penetrate the second semiconductor substrate.

9. The semiconductor package device of claim 8 ,
wherein a gap is present between the under-fill and a bottom surface of the first trench.

10. The semiconductor package device of claim 8 , further comprising:
a plurality of second trenches formed at a lower portion of the first semiconductor chip and vertically overlapping the edge region of the first semiconductor chip,
wherein the under-fill fills a portion of each of the plurality of second trenches.

11. The semiconductor package device of claim 1 ,
wherein the at least one first trench includes a trench including a first portion extending in the first direction, a second portion being bent at a location that vertically overlaps a corner of the semiconductor package, and a third portion extending in a second direction parallel to the top surface of the package substrate, the second direction intersecting the first direction, and
wherein the third portion connects the first portion and the second portion with each other.

12. The semiconductor package device of claim 1 , further comprising:
a third semiconductor chip on the interposer,
wherein the third semiconductor chip is spaced apart from the semiconductor package.

13. The semiconductor package device of claim 12 , further comprising:
a heat sink on the semiconductor package,
wherein a thickness of the heat sink is between about 0.2 mm and about 1.2 mm.

14. The semiconductor package device of claim 12 , wherein
a top surface of the semiconductor package and a top surface of the third semiconductor chip are located at substantially the same level,
the semiconductor package device further comprises a heat sink on the semiconductor package and the third semiconductor chip, and
a thickness of the heat sink is between about 0.2 mm and about 1.2 mm.

15. A semiconductor package device, comprising:
a package substrate;
an interposer on the package substrate;
a semiconductor package on the interposer; and
an under-fill between the interposer and the semiconductor package,
wherein the interposer includes:
a silicon substrate;
a wiring layer on the silicon substrate; and
an upper pad on the wiring layer,

wherein the wiring layer includes:
a dielectric layer provided with a plurality of concave portions at an upper portion of the dielectric layer, the plurality of concave portions vertically overlapping an edge region of the semiconductor package; and
a wiring structure in the dielectric layer,

wherein the wiring structure includes a via part in contact with the upper pad, and
wherein a depth of each of the concave portions is less than a thickness of the via part.

16. The semiconductor package device of claim 15 , wherein
each of the plurality of concave portions has a hole shape, and
the plurality of concave portions are arranged in a first direction parallel to a top surface of the package substrate.

17. The semiconductor package device of claim 15 ,
wherein the under-fill fills at least a portion of each of the plurality of concave portions.

18. The semiconductor package device of claim 15 ,
wherein, when viewed in a plan view, the plurality of concave portions are spaced apart from the upper pad.

19. The semiconductor package device of claim 15 ,
wherein the semiconductor package includes:
a first semiconductor chip;
a plurality of second semiconductor chips stacked on the first semiconductor chip; and
a plurality of adhesive layers disposed in a space between the first semiconductor chip and a lowermost second semiconductor chip of the plurality of second semiconductor chips and between spaces between two adjacent second semiconductor chips of the plurality of second semiconductor chips, respectively,

wherein the first semiconductor chip includes:
a first semiconductor substrate; and
a plurality of first through electrodes that penetrate the first semiconductor substrate, and

wherein each of the plurality of second semiconductor chips includes:
a second semiconductor substrate; and
a plurality of second through electrodes that penetrate the second semiconductor substrate.

20. A semiconductor package device, comprising:
a package substrate;
an interposer on the package substrate;
a plurality of semiconductor packages on the interposer, each of the plurality of semiconductor packages including a first semiconductor chip and a plurality of second semiconductor chips that are sequentially stacked on the first semiconductor chip; and
an under-fill between the interposer and the first semiconductor chip,
wherein each of the first semiconductor chip and the plurality of second semiconductor chips includes a plurality of through electrodes,
wherein

Assignees

• Samsung Electronics Co Ltd

Inventors

• Noh Hyunggyun
• Bae Gun-Hee
• Pae Sangwoo
• Bae Jinsoo
• Choi Deok-Seon
• Choi Il-Joo

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title