Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device

Patent metadata

Field	Value
Publication number	US-11735250-B2
Application number	US-202117395964-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Feb 4, 2021
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of word lines;
a bit line;
a plurality of memory cells connected to the bit line and one of the plurality of word lines;
a sense amplifier, connected to the bit line; and
a control portion configured to control timing of activating the sense amplifier according to a word-line activation signal for activating one of the plurality of the word lines, wherein when a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls a delay time from a time point when the word-line activation signal is valid to a time point when the sense amplifier is activated to be longer,
wherein the control portion comprises a first MOS capacitor and a second MOS capacitor,
wherein when the position of the activated word line among the plurality of word lines is closer to the sense amplifier, the control portion charges the first and second MOS capacitors to control the timing of activating the sense amplifier,
wherein when the position of the activated word line among the plurality of word lines is farther away from the sense amplifier, the control portion charges one of the first MOS capacitor and the second MOS capacitor to control the timing of activating the sense amplifier.

2. The semiconductor memory device as claimed in claim 1 , wherein according to a signal representing the activated word line among the plurality of the word lines, the control portion controls the timing of activating the sense amplifier.

3. The semiconductor memory device as claimed in claim 1 , wherein the control portion comprises:
a circuit portion configured to delay a signal for activating the sense amplifier when the word-line activation signal is input, such that when the position of the activated word line is closer to the sense amplifier, the delay time is longer.

4. The semiconductor memory device as claimed in claim 1 , wherein when the plurality of word lines are classified into a plurality of groups according to the distance between the plurality of word lines and the sense amplifier, the control portion controls the timing of activating the sense amplifier based delay amount set for the group which the activated word line among the plurality of word lines is classified into, such that the set delay amount is greater as the distance between the group and the sense amplifier is shorter.

5. The semiconductor memory device as claimed in claim 4 , wherein information is used to identify the group into which the activated word line among the plurality of word lines is classified and the information comprises a signal representing the activated word line among the plurality of word lines.

6. A semiconductor memory device comprising:
a plurality of word lines divided into a plurality of groups;
a first bit line;
a plurality of memory cells connected to the first bit line and one of the plurality of word lines;
a first sense amplifier connected to the first bit line; and
a control portion configured to receive a row address signal, receive a word-line activation signal for activating one of the plurality of the word lines, determine which group a to-be-activated word line belongs according to the row address signal, and control timing of activating the first sense amplifier according to the word-line activation signal,
wherein when a position of the group of the to-be-activated word line is closer to the first sense amplifier, the control portion controls a delay time from a time point when the word-line activation signal is valid to a time point when the first sense amplifier is activated to be longer,
wherein the control portion comprises a first MOS capacitor and a second MOS capacitor,
wherein when the position of the group of the to-be-activated word line is closer to the sense amplifier, the control portion charges the first and second MOS capacitors to control the timing of activating the sense amplifier,
wherein when the position of the group of the to-be-activated word line is farther away from the sense amplifier, the control portion charges one of the first MOS capacitor and the second MOS capacitor to control the timing of activating the sense amplifier.

7. The semiconductor memory device as claimed in claim 6 , wherein the control portion comprises:
a circuit portion configured to delay a signal for activating the first sense amplifier when the row address signal and the word-line activation signal are input, such that when the position of the group of the to-be-activated word line is closer to the first sense amplifier, the delay time is longer.

8. The semiconductor memory device as claimed in claim 6 , further comprising:
a second bit line; and
a second sense amplifier connect to the second bit line,
wherein when the position of the group of the to-be-activated word line is closer to the second sense amplifier, the control portion controls a delay time from the time point when the word-line activation signal is valid to a time point when the second sense amplifier is activated to be longer.

9. The semiconductor memory device as claimed in claim 8 , wherein the plurality of memory cells are arranged as an array, the first sense amplifier is disposed on a first side of the array, and the second sense amplifier is disposed on a second side of the array opposite to the first side.

10. The semiconductor memory device as claimed in claim 8 , wherein the plurality of word lines extend in a first direction, the first and second bit lines extend in a second direction, and the second direction is perpendicular to the first direction.

Assignees

• Winbond Electronics Corp

Inventors

• Sato Takahiko

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title