Memory device with split power supply capability

US11735232B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11735232-B2
Application numberUS-202117202326-A
CountryUS
Kind codeB2
Filing dateMar 15, 2021
Priority dateMar 15, 2021
Publication dateAug 22, 2023
Grant dateAug 22, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory device, comprising: a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers; wherein at least one of the first set of power supplies and the second set of power supplies are configurable to provide an adjustable supply voltage or supply current, so as to satisfy a voltage or current requirement of the corresponding one of the first number of memory chips and the second number of memory chips. 2. The memory device of claim 1 , wherein each of the first power module and the second power module comprises a power management chip and a plurality of peripheral electrical components in electrical connection with the power management chip. 3. The memory device of claim 1 , wherein the memory device further comprises: a first channel for coupling the first number of memory chips to a host device external to the memory device; and a second channel for coupling the first second of memory chips to the host device. 4. The memory device of claim 3 , wherein the first channel and the second channel are both double data rate (DDR) channels. 5. The memory device of claim 1 , wherein each of the first number of memory chips and the second number of memory chips comprises a rank of memory chips. 6. The memory device of claim 1 , wherein each of the first number of memory chips and the second number of memory chips comprises at least two ranks of memory chips. 7. The memory device of claim 1 , wherein the first power module and the second power module are disposed at two opposing ends of the printed circuit board, and each being adjacent to one of the first number of memory chips and the second number of memory chips. 8. The memory device of claim 1 , wherein the first power module and the second power module are both disposed at a central portion of the printed circuit board between the first number of memory chips and the second number of memory chips. 9. The memory device of claim 1 , wherein the memory device further comprises a double data rate (DDR) interface via which the memory chips are coupled to a host device. 10. The memory device of claim 1 , wherein the memory chips are volatile memory chips. 11. The memory device of claim 1 , wherein the memory device is an unbuffered dual inline memory module (UDIMM) or a small outline dual inline memory module (SODIMM).

Assignees

Inventors

Classifications

  • G11C5/147Primary

    Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

  • Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

  • associated with surface mounted components · CPC title

  • Memory · CPC title

  • G11C5/141Primary

    Battery and back-up supplies · CPC title

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Frequently asked questions

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What does patent US11735232B2 cover?
A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips…
Who is the assignee on this patent?
Montage Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G11C5/147. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 22 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).