Integrated circuit chip device and related product

Patent metadata

Field	Value
Publication number	US-11734548-B2
Application number	US-201916698108-A
Country	US
Kind code	B2
Filing date	Nov 27, 2019
Priority date	Dec 30, 2017
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

First claim

What is claimed is:

1. An integrated circuit chip device, comprising a primary processing circuit and a plurality of basic processing circuits, wherein
the plurality of basic processing circuits are arranged in an array, and each basic processing circuit is connected to an adjacent basic processing circuit; the primary processing circuit is connected to k basic processing circuits of the plurality of basic processing circuits, wherein the k basic processing circuits include: n basic processing circuits in a first row, n basic processing circuits in an m th row, and m basic processing circuits in a first column;
the plurality of basic processing circuits include a compression mapping circuit configured to perform compression on each data in a neural network operation;
the primary processing circuit is configured to perform each successive operation of the neural network operation and transmit the data to the k basic processing circuits;
the k basic processing circuits are configured to forward data between the primary processing circuit and the plurality of the basic processing circuits; and
the plurality of basic processing circuits are configured to control whether to start the compression mapping circuit to perform compression on the transmitted data according to an operation of the transmitted data, perform the operation of the neural network in parallel according to compressed transmitted data, and transmit the compressed transmitted data to the primary processing circuit through the k basic processing circuits connected to the primary processing circuit,
the primary processing circuit is configured to obtain data blocks to be computed and an operation instruction, divide the data blocks to be computed into a data block for distribution and a data block for broadcasting according to the operation instruction, split the data block for distribution to obtain a plurality of basic data blocks, distribute the plurality of basic data blocks to the k basic processing circuits connected to the primary processing circuit, and broadcast the data block for broadcasting to the k basic processing circuits connected to the primary processing circuit;
the plurality of basic processing circuits are configured to control a starting of the compression mapping circuit so as to perform compression on the basic data blocks and the data block for broadcasting according to the received basic data blocks, the data block for broadcasting, and the operation instruction, then perform an inner product operation on compressed basic data blocks and a compressed data block for broadcasting to obtain an operation result, and transmit the operation result to the primary processing circuit through the k basic processing circuits;
the primary processing circuit is configured to process the operation result to obtain the data blocks to be computed and an instruction result of the operation instruction;
wherein the data block for distribution and the data block for broadcasting are at least one input neuron and/or one weight.

2. The integrated circuit chip device of claim 1 , wherein the compression mapping circuit includes a second sparse processing unit, a third sparse processing unit, and a connection relation processing unit;
wherein the second sparse processing unit is configured to receive third input data, obtain first connection relation data according to the third input data, and transmit the first connection relation data to the connection relation processing unit;
the third sparse processing unit is configured to receive fourth input data, obtain second connection relation data according to the fourth input data, and transmit the second connection relation data to the connection relation processing unit;
the connection relation processing unit is configured to obtain third connection relation data according to the first connection relation data and the second connection relation data, and transmit the third connection relation data to a second data processing unit;
the second data processing unit is configured to compress the third input data and the fourth input data according to the third connection relation data after receiving the third input data, the fourth input data and the third connection relation data, so as to obtain fourth output data and fifth output data; wherein
when the third input data includes at least one input neuron and the fourth input data includes at least one weight, the first connection relation data is connection relation data of the input neuron, and the second connection relation data is connection relation data of the weight, the fourth output data is a processed input neuron, and the fifth output data is a processed weight; when the third input data includes at least one weight, and the fourth input data includes at least one input neuron, the first connection relation data is connection relation data of the weight, the second connection relation data is connection relation data of the input neuron, the fourth output data is a processed weight, and the fifth output data is a processed input neuron.

3. The integrated circuit chip device of claim 2 , wherein
the connection relation data of the input neuron and the connection relation data of the weight are composed of a string or a matrix represented by 0 and 1, and are independent of an output neuron; or
the connection relation data of the input neuron and the connection relation data of the weight are represented in a form of a direct index or a stride index;
wherein, when the connection relation data of the input neuron is represented in the form of the direct index, the connection relation data is a string composed of 0 and 1, wherein 0 indicates that an absolute value of the input neuron is less than or equal to a first threshold, and 1 indicates that an absolute value of the input neuron is greater than the first threshold;
when the connection relation data of the input neuron is represented in the form of the stride index, the connection relation data is a string composed of a distance value between an input neuron whose absolute value is greater than the first threshold and a previous input neuron whose absolute value is greater than the first threshold;
when the connection relation data of the weight is represented in the form of the direct index, the connection relation data is a string composed of 0 and 1, where 0 indicates that an absolute value of the weight is less than or equal to a second threshold, that is, an input neuron corresponding to the weight is not connected to an output neuron corresponding to the weight, and 1 indicates that the absolute value of the weight is greater than the second threshold, that is, the input neuron corresponding to the weight is connected to the output neuron corresponding to the weight; the connection relation data of the weight represented by the direct index form has two representation orders: a string of 0 and 1 composed of connection state of each output neuron and all input neurons for representing the connection relation data of the weight; or a string of 0 and 1 composed of connection state of each input neuron and all output neurons for representing the connection relation data of the weight; and
when the connection relation data of the weight is represented in the form of the stride index, the connection relation data is a string composed of a distance value between an input neuron connected to an output neuron and a previous input neuron connected to the output neuron.

4. The integrated circuit chip device of claim 3 , wherein
when the first connection relation data and the second connection data are represented in the form of the stride index, and a string representing the first connection relation data and the second connection relation data are stored in order of physical address from lowest to highest, the

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Liu Shaoli
• Song Xinkai
• Wang Bingrui
• Zhang Yao
• Hu Shuai

Classifications

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/082

  modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• H03M7/70

  Type of the data to be coded, other than image and sound · CPC title