Matrix tiling to accelerate computing in redundant matrices

US11734225B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11734225-B2
Application numberUS-202016945295-A
CountryUS
Kind codeB2
Filing dateJul 31, 2020
Priority dateFeb 8, 2019
Publication dateAug 22, 2023
Grant dateAug 22, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.

First claim

Opening claim text (preview).

What is claimed is: 1. A non-transitory machine readable medium, including instructions that when executed by a processor causes the processor to: identify at least one unique submatrix in an input matrix; iteratively load values of elements of the at least one submatrix into an array of processors; apply a vector to the loaded values of elements of each of the array of processors; add outputs of the array processors according to a location of the at least one unique submatrix at the input matrix. 2. The non-transitory machine readable medium of claim 1 , further comprising instructions to generate a new vector based on the added outputs. 3. The non-transitory machine readable medium of claim 2 , wherein generating the new vector comprises filtering the added outputs. 4. The non-transitory machine readable medium of claim 1 , further comprising instructions to apply the new vector to the loaded values of elements of each of the array of processors. 5. The non-transitory machine readable medium of claim 1 , wherein each row of the at least one submatrix is processed in order. 6. The non-transitory machine readable medium of claim 1 , wherein each row of the at least one submatrix is processed concurrently. 7. A method comprising: identifying unique submatrices in a matrix; loading values of elements of each unique submatrix into an array processor of a plurality of array processors; applying a vector to the loaded values of each of the array processors; and adding outputs of the array processors according to a location of the unique submatrices in the matrix. 8. The method of claim 7 , wherein each array processor comprises N row lines, N column lines, and N2 memory cells each coupled between a respective combination of one of the row lines and one of the column lines. 9. The method of claim 8 , further comprising storing values of elements of the matrix at the memory cells.

Assignees

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Classifications

  • Array of vector units · CPC title

  • Arithmetic instructions · CPC title

  • Neural networks · CPC title

  • G06F17/16Primary

    Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

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What does patent US11734225B2 cover?
a Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations …
Who is the assignee on this patent?
Hewlett Packard Entpr Dev Lp
What technology area does this patent fall under?
Primary CPC classification G06F15/8092. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 22 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).