Hardware assisted fine-grained data movement

Patent metadata

Field	Value
Publication number	US-11734059-B2
Application number	US-202016824601-A
Country	US
Kind code	B2
Filing date	Mar 19, 2020
Priority date	Mar 19, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

First claim

What is claimed is:

1. A method implemented at a processor, comprising:
receiving, a task dependency graph representative of a plurality of tasks;
receiving task data requirements that correspond to each task of the plurality of tasks;
performing a task dependency assessment of the task dependency graph and the task data requirements; and
based on the task dependency assessment, scheduling for execution a first task of the plurality of tasks and a proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the proxy object occurs while the first task is being executed.

2. The method of claim 1 , wherein:
the task dependency assessment indicates a task dependency of each task in the plurality of tasks and a set of the plurality of proxy objects that are required for each task to execute.

3. The method of claim 2 , further comprising:
using the task dependency of each task in the plurality of tasks to schedule the plurality of tasks such that a memory transfer of proxy objects representative of data-blocks from a central processing unit (CPU) memory to a graphics processing unit (GPU) memory occurs during the execution of a predecessor task.

4. The method of claim 1 , further comprising:
generating a first mapping of the plurality of tasks represented in the task dependency graph to a plurality of data blocks required for each task of the plurality of tasks.

5. The method of claim 4 , further comprising:
using the first mapping to schedule the plurality of proxy objects required for each task of the plurality of tasks according to a first order of the proxy objects in the first mapping.

6. The method of claim 5 , further comprising:
generating a second mapping of the plurality of tasks represented in the task dependency graph to a task dependency of each task and a total number of predecessors of each task.

7. The method of claim 6 , further comprising:
using the second mapping of the plurality of tasks represented in the task dependency graph to schedule the plurality of tasks such that each successor task of the plurality of tasks is scheduled after a corresponding predecessor task.

8. The method of claim 7 , further comprising:
generating a third mapping of a plurality of proxy objects to a plurality of tasks that access the plurality of data blocks.

9. The method of claim 8 , further comprising:
using the third mapping of the plurality of tasks represented in the task dependency graph to schedule the plurality of tasks and the plurality of data blocks.

10. The method of claim 1 , further comprising:
generating a task-dispatch list that includes a first task of the plurality of tasks to be scheduled, the plurality of tasks being placed in the task-dispatch list based on an execution order; and
scheduling the plurality of tasks and a plurality of data blocks based on the execution order of the task-dispatch list.

11. The method of claim 1 , wherein a proxy object is an object that contains information of a data block of a specific size.

12. A processing system including at least one processor, comprising:
a task scheduling unit; and
a compute unit coupled to the task scheduling unit, wherein the task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of a plurality of tasks of the task dependency graph, and based on the task dependency assessment, schedules a first task of the plurality of tasks and a second data block of a plurality of data blocks specified by the task data requirements such that a memory transfer of the second data block of the plurality of sub-data blocks occurs while the first task is being executed.

13. The processing system of claim 12 , wherein:
the task dependency assessment reveals a task dependency of each task in the plurality of tasks and which plurality of data blocks of the plurality of data blocks are required for each task to execute.

14. The processing system of claim 13 , wherein:
the task dependency of each task in the plurality of tasks is used to to schedule the plurality of tasks such that a memory transfer of proxy objects representative of data-blocks from a central processing unit (CPU) memory to a graphics processing unit (GPU) memory occurs during the execution of a predecessor task.

15. The processing system of claim 14 , further comprises:
a task scheduling unit that generates a first mapping of the plurality of tasks represented in the task dependency graph to a plurality of data blocks required for each task of the plurality of tasks.

16. The processing system of claim 15 , wherein:
the first mapping is used to schedule the plurality of data blocks required for each task of the plurality of tasks according to a first order of the data blocks in the first mapping.

17. The processing system of claim 16 , wherein:
the task scheduling unit generates a second mapping of the plurality of tasks represented in the task dependency graph to the task dependency of each task and a total number of predecessors of each task.

18. The processing system of claim 17 , wherein:
the second mapping of the plurality of tasks represented in the task dependency graph is used to schedule the plurality of tasks such that each successor task of the plurality of tasks is scheduled after a corresponding predecessor task.

Assignees

• Advanced Micro Devices Inc

Inventors

• Hassaan Muhammad Amber
• Kaushik Anirudh Mohan
• Puthoor Sooraj
• Ravi Gokul Subramanian
• Beckmann Bradford
• Aji Ashwin

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F16/9024 Primary

  Graphs; Linked lists (G06F16/9027 takes precedence) · CPC title

• G06F2209/486

  Scheduler internals · CPC title