Data processing system and method for reading instruction data of instruction from memory including a comparison stage for preventing execution of wrong instruction data

Patent metadata

Field	Value
Publication number	US-11733879-B2
Application number	US-202217965796-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Dec 4, 2020
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

First claim

What is claimed is:

1. A data processing system, comprising:
a memory, including a first region and a second region;
a read data check circuit, coupled to the second region of the memory to receive a dummy data, and comparing the dummy data to a hardwire data; and
a microprocessor, coupled to the memory and the read data check circuit, configured to access the memory using an instruction address to fetch instruction data, receive the instruction data from the first region and a comparison result from the read data check circuit in response to the instruction address, and determine whether to execute the instruction data corresponding to the instruction address according to the comparison result, wherein the hardwire data having a bit pattern represents a command to control the microprocessor.

2. The data processing system of claim 1 , wherein when the comparison result indicates that the dummy data matches the hardwire data, the microprocessor determines that the instruction data received from the first region of the memory corresponds to the instruction address and fetches another instruction address of a subsequent instruction from the memory.

3. The data processing system of claim 1 , wherein the microprocessor accesses the memory again using the instruction address when the comparison result indicates that the dummy data does not match the hardwire data.

4. The data processing system of claim 1 , wherein the microprocessor executes a plurality of instructions using an instruction pipeline to process the instructions in an order that are received, wherein the microprocessor is configured to stall the instruction pipeline when the comparison result indicates that the dummy data does not match the hardwire data.

5. The data processing system of claim 1 , wherein the read data check circuit comprises:
a comparator coupled between the second region of the memory and the microprocessor, and
a multiplexer coupled between the first region of the memory and the microprocessor, and configured to receive the instruction data from the first region of the memory and the hardwire data, and to select the hardwire data or the instruction data received from the memory as an output to the microprocessor according to a read fail signal.

6. The data processing system of claim 5 , wherein the read fail signal is set according to a predetermined number of maximum attempts for reading the memory, and the hardwire data is selected as the output to the microprocessor to stop the execution of the instruction address.

7. The data processing system of claim 1 , wherein the hardwire data is a flush instruction to flush an instruction pipeline of the microprocessor.

8. The data processing system of claim 1 , further comprising
a sense amplifier circuit, coupled to the memory, and reading the instruction data from the first region of the memory and the dummy data from the second region of the memory, wherein the instruction data is output to the microprocessor and the dummy data is output to the read data check circuit.

9. The data processing system of claim 1 , wherein the microprocessor is configured to process a first instruction and a second instruction in an instruction pipeline, wherein the instruction pipeline includes an instruction fetch stage, an instruction decode stage, a comparison stage and an execution stage, wherein the comparison stage stalls the instruction pipeline and starts over the instruction fetch stage on the first instruction when the comparison result indicates that the dummy data does not match the hardwire data.

10. The data processing system of claim 9 , wherein the microprocessor continues to process the second instruction when determined that the dummy data matches the hardwire data in the comparison stage of the first instruction.

11. The method of claim 1 , wherein the hardwire data is predetermined and stored in a storage circuit other than the memory, and the memory is a non-volatile memory.

12. A method of reading instruction data of an instruction from a memory, comprising:
receiving a first instruction address corresponding to a first instruction;
obtaining, from the memory, a first instruction data and a first dummy data based on the first instruction address;
comparing the first dummy data to a hardwire data, wherein the hardwire data having a bit pattern represents a command to control a microprocessor;
providing the first instruction data to the microprocessor when determined that the first dummy data matches the hardwire data.

13. The method of claim 12 , further comprising:
providing the first instruction data corresponding to the first instruction address to the microprocessor when determined that the first dummy data matches the hardwire data.

14. The method of claim 12 , further comprising:
receiving an instruction pipeline including the first instruction and a second instruction arranged sequentially before receiving the first instruction address;
receiving a second instruction address of the second instruction subsequent the first instruction after determined that the first dummy data matches the hardwire data,
stalling the instruction pipeline after determined that the first dummy data does not match the hardwire data.

15. The method of claim 12 , further comprising:
providing a first signal to the microprocessor to indicate that the memory is not ready for a second instruction subsequent to the first instruction when determined that the first dummy data does not match the hardwire data.

16. The method of claim 12 , further comprising:
incrementing a read fail counter when determined that the first dummy data does not match the hardwire data.

17. The method of claim 16 , further comprising:
determining whether the read fail counter has reached a predetermined number of read attempts.

18. The method of claim 17 , further comprising:
repeatedly obtaining the first instruction data and the first dummy data from the memory based on the first instruction address until the read fail counter reaches the predetermined number of read attempts.

19. The method of claim 17 , further comprising:
providing the hardware data to the microprocessor when determined that the read fail counter has reached the predetermined number of read attempts.

20. The method of claim 12 , further comprising:
receiving a second instruction address of the second instruction subsequent the first instruction after determined that the first dummy data matches the hardwire data.

Assignees

• Winbond Electronics Corp

Inventors

• Michael Oron
• Suito Katsutoshi

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1407 Primary

  Checkpointing the instruction stream · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title