Near-memory compute module

Patent metadata

Field	Value
Publication number	US-11733870-B2
Application number	US-201916249109-A
Country	US
Kind code	B2
Filing date	Jan 16, 2019
Priority date	Jan 7, 2014
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Disclosed herein are systems having an integrated circuit device disposed within an integrated circuit package having a periphery, and within this periphery a transaction processor is configured to receive a combination of signals (e.g., using a standard memory interface), and intercept some of the signals to initiate a data transformation, and forward the other signals to one or more memory controllers within the periphery to execute standard memory access operations (e.g., with a set of DRAM devices). The DRAM devices may or may not be in within the package periphery. In some embodiments, the transaction processor can include a data plane and control plane to decode and route the combination of signals. In other embodiments, off-load engines and processor cores within the periphery can support execution and acceleration of the data transformations.

First claim

What is claimed is:

1. A transactional memory controller device comprising:
a transaction processor coupled to a first physical interface to send and receive first signals to and from a first memory controller of a host controller over a system bus based on an instruction from a central processing unit (CPU) of the host controller, the transaction processor comprising a data buffer to buffer the first signals; and
a second memory controller coupled to the transaction processor and to a second physical interface to send and receive second signals to and from a plurality of dynamic random access memory (DRAM) devices, wherein the transaction processor is to:
decode a first command in a first portion of the first signals;
initiate, in response to the first command, a set of data transformation operations on a dataset stored in at least one DRAM device of the plurality of DRAM devices based on data received from the first memory controller;
send results of the set of data transformation operations to the first memory controller via the first physical interface, wherein the set of data transformation operations are performed by the second memory controller and the transaction processor without interaction with the first memory controller;
decode a second command in a second portion of the first signals to perform an access operation, wherein the access operation is a write access operation or a read access operation; and
forward the second command to perform the access operation to the second memory controller, the second memory controller to initiate execution of the access operation with the plurality of DRAM devices via the second physical interface.

2. The transactional memory controller device of claim 1 , further comprising an off-load engine coupled to the transaction processor, wherein the off-load engine is to accelerate the set of data transformation operations by performing one or more data transformation operations.

3. The transactional memory controller device of claim 2 , wherein the one or more data transformation operations are at least a compress operation, a uncompress operation, an encryption operation, a decryption operation, a Galois field arithmetic operation, a hashing operation, or an indexing operation.

4. The transactional memory controller device of claim 1 , further comprising an off-load engine coupled to the transaction processor, wherein the transaction processor and the off-load engine perform the set of data transformation operations as parallel background processing.

5. The transactional memory controller device of claim 1 , wherein the first physical interface is a standard memory interface.

6. The transactional memory controller device of claim 1 , wherein the first physical interface is a JEDEC DDR4 DRAM standard interface.

7. The transactional memory controller device of claim 1 , wherein the transaction processor comprises a set of data buffers to send and receive the first signals to and from the first memory controller and send and receive the second signals to and from the plurality of DRAM devices, wherein the set of data buffers allow the plurality of DRAM devices to emulate a type of Dual In-Line Memory Module (DIMM) selected from an un-buffered DIMM type (UDIMM), a load-reduction DIMM type (LRDIMM), and a registered DIMM type (RDIMM).

8. The transactional memory controller device of claim 1 , wherein the transaction processor is to communicate with the first memory controller using the first physical interface so as to appear as a physical memory to the first memory controller.

9. The transactional memory controller device of claim 1 , further comprising an integrated circuit package periphery, wherein the transaction processor and the second memory controller reside within the integrated circuit package periphery.

10. The transactional memory controller device of claim 9 , wherein the transaction processor comprises:
data plane memory;
control plane memory; and
data buffers coupled to the first physical interface.

11. The transactional memory controller device of claim 10 , further comprising:
a plurality of processor cores;
a plurality of off-load engines;
a third memory controller; and
a non-volatile memory controller, wherein the plurality of processor cores, the plurality of off-load engines, the third memory controller, and the non-volatile memory controller reside within the integrated circuit package periphery.

12. The transactional memory controller device of claim 1 , further comprising an integrated circuit package periphery, wherein the transaction processor, the second memory controller, and the plurality of DRAM devices reside within the integrated circuit package periphery.

13. The transactional memory controller device of claim 12 , wherein the transaction processor comprises:
data plane memory;
control plane memory; and
data buffers coupled to the first physical interface.

14. The transactional memory controller device of claim 13 , further comprising:
a plurality of processor cores;
a plurality of off-load engines;
a third memory controller;
a non-volatile memory controller; and
a non-volatile memory device coupled to the non-volatile memory controller, wherein the plurality of processor cores, the plurality of off-load engines, the third memory controller, the non-volatile memory controller, and the non-volatile memory device reside within the integrated circuit package periphery.

15. The transactional memory controller device of claim 1 , wherein the transaction processor is further to:
intercept the first portion of the first signals;
determine, based on the first command, a set of one or more instructions to perform the set of data transformation operations;
execute the set of one or more instructions during one or more wait times after the first portion is intercepted and before the results from the set of data transformation operations are expected by the first memory controller; and
determine the results from execution of the set of one or more instructions.

16. The transactional memory controller device of claim 15 , wherein the transaction processor is further to:
intercept the second portion of the first signals, wherein the access operation is decoded in the second portion of the first signals;
forward the second portion of the first signals to the second memory controller to initiate execution of the access operation as the write access operation or the read access operation; and
when the second portion corresponds to the write access operation, receive write data associated with the write access operation from the first memory controller and forward the write data to the second memory controller; and
when the second portion corresponds to the read access operation, receive read data associated with the read access operation from the second memory controller and forward, to the first memory controller, the read data during one or more wait times after the first portion of the first signals is intercepted and before the results of the set of data transformation operations are expected by the first memory controller.

17. The transactional memory controller device of claim 1 , wherein the second physical interface is a standard memory interface.

18. The transactional memory controller device of claim 1 , wherein the second physical interface is a JEDEC DDR4 DRAM standard interface.

19. A compute dual in-line memory module comprising:
a plurality of dynamic random access memory (DRAM) devices;
a transaction processor coupled to a

Assignees

• Rambus Inc

Inventors

• Wang David
• Saxena Nirmal

Classifications

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title