Semiconductor device including non-volatile memory, a bias current generator and an on-chip termination resistor, method of fabricating the same and method of operating the same
US-10845837-B2 · Nov 24, 2020 · US
US11733727B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11733727-B2 |
| Application number | US-202217680386-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 25, 2022 |
| Priority date | Apr 14, 2021 |
| Publication date | Aug 22, 2023 |
| Grant date | Aug 22, 2023 |
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Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.
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What is claimed is: 1. An integrated circuit comprising: a peripheral circuit; and a first bias current generating circuit, wherein the first bias current generating circuit includes: a first amplifier configured to receive a reference voltage and a first voltage, and to amplify a difference between the first voltage and the reference voltage to output a first output voltage; a first bias current generator configured to receive the first output voltage, and to output a first bias current in response to the first output voltage; a variable resistor configured to receive the first bias current from the first bias current generator, and to output said first voltage in response to the first bias current and a calibration code; a second bias current generator configured to receive the first output voltage, and to output a second bias current to the peripheral circuit in response to the first output voltage; and a third bias current generator configured to receive the first output voltage, and to output a third bias current to an external device through a first pad in response to the first output voltage. 2. The integrated circuit of claim 1 , further comprising: an electrical fuse configured to store the calibration code, wherein the calibration code stored in the electrical fuse is applied to the variable resistor. 3. The integrated circuit of claim 2 , wherein the peripheral circuit receives the calibration code from the external device through a second pad and stores the received calibration code in the electrical fuse. 4. The integrated circuit of claim 1 , wherein the peripheral circuit transfers the calibration code to the variable resistor. 5. The integrated circuit of claim 4 , wherein the peripheral circuit receives the calibration code from the external device through a second pad and transfers the received calibration code to the variable resistor. 6. The integrated circuit of claim 1 , further comprising: a second bias current generating circuit, wherein the second bias current generating circuit includes: a second amplifier configured to receive the reference voltage and a second voltage, and to amplify a difference between the second voltage and the reference voltage to output a second output voltage; a fourth bias current generator configured to receive the second output voltage, and to output a fourth bias current in response to the second output voltage; a first resistor configured to receive the fourth bias current from the fourth bias current generator, and to output the second voltage in response to the fourth bias current; and a fifth bias current generator configured to receive the second output voltage, and to output a fifth bias current to the peripheral circuit in response to the second output voltage. 7. The integrated circuit of claim 6 , wherein the second bias current generating circuit further includes: a sixth bias current generator configured to receive the second output voltage, and to output a sixth bias current in response to the second output voltage; and a second resistor configured to receive the sixth bias current from the sixth bias current generator, and to output a third voltage in response to the sixth bias current. 8. The integrated circuit of claim 7 , further comprising: a third amplifier configured to receive a voltage from an output node of the third bias current generator in the first bias current generating circuit and the third voltage, and to amplify a difference between the voltage of the output node and the third voltage to output a third output voltage. 9. The integrated circuit of claim 8 , further comprising: calibration logic configured to receive the third output voltage, and to generate the calibration code from the third output voltage. 10. The integrated circuit of claim 6 , further comprising: a third amplifier configured to receive a voltage of an output node of the third bias current generator in the first bias current generating circuit and the reference voltage, and to amplify a difference between the voltage from the output node and the reference voltage to output a third output voltage. 11. The integrated circuit of claim 10 , further comprising: calibration logic configured to receive the third output voltage, and to generate the calibration code from the third output voltage. 12. The integrated circuit of claim 11 , wherein the calibration code output from the calibration logic is transferred to the variable resistor. 13. The integrated circuit of claim 11 , further comprising: an electrical fuse, wherein the calibration code output from the calibration logic is transferred to the peripheral circuit, and the peripheral circuit stores the calibration code transferred from the calibration logic in the electrical fuse. 14. A bias current generating device comprising: an electrical fuse configured to store a calibration code; a first amplifier configured to receive a reference voltage and a first voltage, and to amplify a difference between the first voltage and the reference voltage to output a first output voltage; a first bias current generator configured to receive the first output voltage, and to output a first bias current in response to the first output voltage; a variable resistor configured to receive the first bias current from the first bias current generator, to receive the calibration code from the electrical fuse, and to output the first voltage in response to the first bias current and the calibration code; a second bias current generator configured to receive the first output voltage, and to output a second bias current to a peripheral circuit in response to the first output voltage; a third bias current generator configured to receive the first output voltage, and to output a third bias current to an external device through a pad in response to the first output voltage; a second amplifier configured to receive the reference voltage and a second voltage, and to amplify a difference between the second voltage and the reference voltage to output a second output voltage; a fourth bias current generator configured to receive the second output voltage, and to output a fourth bias current in response to the second output voltage; a first resistor configured to receive the fourth bias current from the fourth bias current generator, and to output the second voltage in response to the fourth bias current; and a fifth bias current generator configured to receive the second output voltage, and to output a fifth bias current to the peripheral circuit in response to the second output voltage. 15. The bias current generating device of claim 14 , further comprising: a third amplifier configured to receive a voltage of an output node of the third bias current generator and the reference voltage, and to amplify a difference between the voltage of the output node and the reference voltage to output a third output voltage; and calibration logic configured to generate a second calibration code from the third output voltage. 16. The bias current generating device of claim 15 , wherein the second calibration code, the second bias current, and the fourth bias current are transferred to the peripheral circuit, and wherein the second calibration code is stored in the electrical fuse by the peripheral circuit as the calibration code. 17. The bias current generating device of claim 15 , further comprising: a first multiplexer configured to select and output one of an output of the electrical fuse and an output of the peripheral circuit; and a second multiplexer configu
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