Wafer holder

US11732359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11732359-B2
Application numberUS-201816498853-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2018
Priority dateMar 28, 2017
Publication dateAug 22, 2023
Grant dateAug 22, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; and a conductive member embedded in the ceramic base, the conductive member including a circuit portion provided parallel to the wafer-mounting surface, a pull-out portion provided parallel to the wafer-mounting surface and spaced from the circuit portion in a direction opposite to a direction toward the wafer-mounting surface, and a connecting portion configured to electrically connect the circuit portion and the pull-out portion to each other.

First claim

Opening claim text (preview).

The invention claimed is: 1. A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; a first conductive member embedded in the ceramic base, the first conductive member including a first circuit portion provided parallel to the wafer-mounting surface, a first pull-out portion provided parallel to the wafer-mounting surface and spaced from the first circuit portion in a direction opposite to a direction toward the wafer-mounting surface, wherein the first pull-out portion is located in a first layer in a thickness direction of the ceramic base, and a first plurality of connecting portions configured to electrically connect the first circuit portion and the first pull-out portion to each other; a second conductive member embedded in the ceramic base, the second conductive member including at least one second circuit portion provided parallel to the wafer-mounting surface, at least one second pull-out portion provided parallel to the wafer-mounting surface and spaced from the at least one second circuit portion in the direction opposite to the direction toward the wafer-mounting surface, wherein the at least one second pull-out portion is located in a second layer in the thickness direction of the ceramic base, the second layer being spaced from the first layer in the thickness direction, and a second plurality of connecting portions configured to electrically connect the at least one second circuit portion and the at least one second pull-out portion to each other; a cylindrical support configured to support a lower surface of the ceramic base; and an electrode terminal portion connected to the first pull-out portion, wherein a portion of the electrode terminal portion protrudes from the lower surface of the ceramic base and is housed in the cylindrical support, and the first plurality of connecting portions are arranged in a circumferential direction at an outer circumferential portion of the first pull-out portion. 2. The wafer holder according to claim 1 , wherein the first conductive member constitutes an RF electrode. 3. The wafer holder according to claim 1 , wherein each of the first and second conductive members constitutes an RF electrode. 4. The wafer holder according to claim 1 , wherein the ceramic base has a disk shape. 5. The wafer holder according to claim 1 , wherein the cylindrical support has a circular cylindrical shape. 6. The wafer holder according to claim 1 , wherein the first circuit portion and the at least one second circuit portion are located in the same layer in the thickness direction of the ceramic base. 7. The wafer holding according to claim 1 , wherein the first plurality of connecting portions include a ceramic member covered with a metal layer. 8. The wafer holder according to claim 7 , wherein the ceramic member is made of a ceramic material selected from the group consisting of aluminum nitride, silicon nitride, silicon carbide, and aluminum oxide. 9. The wafer holder according to claim 7 , wherein the ceramic base is made of a first ceramic material, and the ceramic member is made of a second ceramic material having substantially the same coefficient of thermal expansion as the first ceramic material. 10. The wafer holder according to claim 7 , wherein the ceramic member is made of the same ceramic material as the ceramic base.

Assignees

Inventors

Classifications

  • H10P72/72Primary

    using electrostatic chucks · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • mainly by conduction · CPC title

  • C23C16/458Primary

    characterised by the method used for supporting substrates in the reaction chamber · CPC title

  • Substrate holders · CPC title

Patent family

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Frequently asked questions

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What does patent US11732359B2 cover?
A wafer holder comprising: a ceramic base having a wafer-mounting surface as an upper surface; and a conductive member embedded in the ceramic base, the conductive member including a circuit portion provided parallel to the wafer-mounting surface, a pull-out portion provided parallel to the wafer-mounting surface and spaced from the circuit portion in a direction opposite to a direction toward …
Who is the assignee on this patent?
Sumitomo Electric Industries
What technology area does this patent fall under?
Primary CPC classification H10P72/72. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 22 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).