Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11729981-B2
Application number	US-202217707469-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Jun 11, 2019
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a stack body in which interlayer insulating films and sacrificial films are alternately stacked;
forming a hole penetrating the stack body;
forming a first material film on an inner wall of the hole;
forming a channel structure in a center region of the hole opened by the first material film;
removing the sacrificial films of the stack body to form opening portions exposing the first material film;
removing exposed regions of the first material film through the opening portions so that the first material film is separated into first material patterns;
forming second material patterns by oxidizing a portion of the first material patterns from an etched surface of each of the first material patterns; and
forming gate electrodes filling the opening portions and extending between the second material patterns.

2. The method of claim 1 , wherein the second material patterns extend to cover edges of the interlayer insulating films facing the channel structure.

3. The method of claim 1 , wherein the gate electrodes include recessed portions in a shape corresponding to the second material patterns.

4. The method of claim 1 , wherein the first material film includes at least one of a silicon oxynitride film (SiON), a silicon nitride film (SiN), and silicon (Si).

5. The method of claim 1 , further comprising:
forming a blocking insulating film on the first material film;
forming a data storage film on the blocking insulating film; and
forming a tunnel insulating film on the data storage film.

6. A method of manufacturing a semiconductor device, the method comprising:
forming a stack body in which interlayer insulating films and sacrificial films are alternately stacked;
forming a hole penetrating the stack body;
forming a first material film on an inner wall of the hole;
forming a memory film on the first material film;
forming a channel structure in a center region of the hole opened by the memory film;
removing the sacrificial films of the stack body to form first opening portions exposing the first material film;
etching the first material film through the first opening portions so that second opening portions are defined between the interlayer insulating films and the memory film;
forming second material patterns in the second opening portions; and
forming gate electrodes filling the first opening portions and extending between the second material patterns.

7. The method of claim 6 , wherein the memory film includes a blocking insulating film formed on the first material film, a data storage film formed on the blocking insulating film, and a tunnel insulating film formed on the data storage film.

8. The method of claim 6 , wherein the first material film includes a silicon oxynitride film (SiON).

9. The method of claim 6 , wherein the second material patterns include a porous insulating material filling the second opening portions.

10. The method of claim 6 , wherein the forming the second material patterns comprises:
forming a second material film along surfaces of the interlayer insulating films so that a void is formed in each of the second opening portions; and
etching the second material film so that the second material patterns remain on edges of the interlayer insulating films facing the channel structure.

11. The method of claim 10 , wherein the gate electrodes are spaced apart from the void by the second material patterns which are in contact with the interlayer insulating films.

Assignees

• Sk Hynix Inc

Inventors

• Seo Moon Sik
• Choi Gil Bok

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10P14/6903

  containing silicon · CPC title