Device and method for managing electromagnetic radiation

US11728398B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11728398-B2
Application numberUS-202016928243-A
CountryUS
Kind codeB2
Filing dateJul 14, 2020
Priority dateAug 23, 2019
Publication dateAug 15, 2023
Grant dateAug 15, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor devices having conductive floating gates superimposed on and/or embedded within a conducting channel for managing electromagnetic radiation in the device. The conductive floating gates can comprise a one- or two-dimensional array of asymmetric structures superimposed on and/or embedded within the conducting channel. The conductive floating gates can comprise Nb 2 N, Ta 2 N, TaN x , NbN x , WN x , or MoN x or any transition metal nitride compound. The device can include a plurality of conductive floating gates on a rear surface of a barrier layer, wherein each of the conductive floating gates might be separately biased for individual tuning. Antennas for capturing or emitting THz or sub-THz radiation could be attached to the device contacts. Terahertz or infrared radiation could be manipulated by driving a current through the conducting channel into a plasmonic boom regime. Additional manipulation of the electromagnetic radiation could be achieved by having antennas with an appropriate phase angle shift.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device having a plurality of separated floating gates directly embedded within a conducting channel within the semiconductor device; wherein each one of the plurality of separated floating gates is spaced-apart from another one of the plurality of separated floating gates within the conducting channel; wherein each of the plurality of separated floating gates has a size smaller than a mean free path of electrons in the semiconductor device. 2. The semiconductor device according to claim 1 , wherein the plurality of separated floating gates comprises a one- or two-dimensional periodic array of asymmetric structures. 3. The semiconductor device according to claim 1 , wherein the plurality of separated floating gates comprises one or more concentric structures surrounding a central source. 4. The semiconductor device according to claim 1 , wherein one or more additional floating gates are isolated front the conducting channel by a barrier layer, wherein the conducting channel is configured for managing electromagnetic radiation within the semiconductor device. 5. The semiconductor device according to claim 1 , wherein at least one of the plurality of separated floating gates comprises Nb 2 N, Ta 2 N, TaN x , NbN x , WN x , MoN x , graphene, or a transition metal nitride ternary compound. 6. The semiconductor device according to claim 1 , wherein at least one of the plurality of separated floating gates comprises semiconducting or metallic nanoparticles or nanocrystals. 7. The semiconductor device according to claim 1 , wherein at least a portion of the plurality of separated floating gates is situated on a rear surface of a barrier layer in the semiconductor device, wherein each of the floating gates in the portion can be separately biased for individual tuning. 8. The semiconductor device according to claim 1 , wherein the semiconductor device further includes at least one antenna attached to device contacts, wherein the at least one antenna is configured to manage THz or sub-THz radiation in the semiconductor device. 9. The semiconductor device according to claim 1 , wherein the semiconductor device further includes at least one antenna attached to device contacts, wherein the at least one antenna is configured to manage radiation in the semiconductor device through an appropriate phase angle shift. 10. The semiconductor device according to claim 1 , wherein at least one of the plurality of separated floating gates comprises superconducting material. 11. A method for managing electromagnetic waves in a semiconductor device, comprising: providing a semiconductor device having a plurality of separated floating gates directly embedded within a conducting channel within the semiconductor device; wherein each one of the plurality of separated floating gates is spaced-apart from another one of the plurality of separated floating gates within the conducting channel; wherein each of the plurality of separated floating gates has a size smaller than a mean free path of electrons in the semiconductor device; the method further comprising modulating, via the plurality of separated floating gates, properties of plasma waves in an electronic field of the semiconductor device. 12. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein the plurality of separated floating gates comprises a one- or two-dimensional periodic array of asymmetric structures. 13. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein the plurality of separated floating gates comprises one or more concentric structures surrounding a central source. 14. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein one or more additional floating gates are isolated from the conducting channel by a barrier layer, wherein the conducting channel is configured for managing electromagnetic radiation within the semiconductor device. 15. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein at least one of the plurality of separated floating gates comprises Nb 2 N, Ta 2 N, TaN x , NbN x , WN x , MoN x , graphene, or a transition metal nitride ternary compound. 16. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein at, least one of the plurality of separated floating gates comprises semiconducting or metallic nanoparticles or nanocrystals. 17. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein at least a portion of the plurality of separated floating gates is situated on a rear surface of a barrier layer in the semiconductor device, wherein each of the floating gates in the portion can be separately biased for individual tuning. 18. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein the semiconductor device further includes at least one antenna attached to device contacts, wherein the at least one antenna is configured to manage THz or sub-THz radiation in the semiconductor device. 19. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein the semiconductor device further includes at least one antenna attached to device contacts, wherein the at least one antenna is configured to manage radiation in the semiconductor device through an appropriate phase angle shift. 20. The method for managing electromagnetic waves in a semiconductor device according to claim 11 , wherein at least one of the plurality of separated floating gates comprises superconducting material.

Assignees

Inventors

Classifications

  • protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

  • of FETs having floating gates · CPC title

  • Floating-gate IGFETs · CPC title

  • X-ray, gamma-ray or corpuscular radiation imagers · CPC title

  • Infrared image sensors · CPC title

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What does patent US11728398B2 cover?
Semiconductor devices having conductive floating gates superimposed on and/or embedded within a conducting channel for managing electromagnetic radiation in the device. The conductive floating gates can comprise a one- or two-dimensional array of asymmetric structures superimposed on and/or embedded within the conducting channel. The conductive floating gates can comprise Nb 2 N, Ta 2 N, TaN x …
Who is the assignee on this patent?
Us Gov Sec Navy
What technology area does this patent fall under?
Primary CPC classification H10D30/6892. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 15 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).