Static random-access memory for deep neural networks

Patent metadata

Field	Value
Publication number	US-11727261-B2
Application number	US-202117518660-A
Country	US
Kind code	B2
Filing date	Nov 4, 2021
Priority date	Sep 21, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.

First claim

What is claimed is:

1. A static random-access memory (SRAM) system comprising a SRAM cell, the SRAM cell comprising:
a write word line;
a first write bit line and a second write bit line;
a read bit line;
a first read word line, a second read word line, a third read word line, and a fourth read word line;
a first inverter comprising an input coupled to a first intermediate node, an output coupled to a second intermediate node, a first voltage input node coupled to a supply voltage, and a second voltage input node coupled to a fixed voltage;
a second inverter comprising an input coupled to the second intermediate node, an output coupled to the first intermediate node, a first voltage input node coupled to the supply voltage, and a second voltage input node coupled to a fixed voltage;
a third inverter comprising an input coupled to the first intermediate node, an output coupled to the read bit line, a first voltage input node coupled to the first read word line, and a second voltage input node coupled to the second read word line;
a fourth inverter comprising an input coupled to the second intermediate node, an output coupled to the read bit line, a first voltage input node coupled to the third read word line, and a second voltage input node coupled to the fourth read word line;
a first switching element comprising a control node coupled to the write word line, a first switching node coupled to the first write bit line, and a second switching node coupled to the first intermediate node; and
a second switching element comprising a control node coupled to the write word line, a first switching node coupled to the second write bit line, and a second switching node coupled to the second intermediate node.

2. The SRAM system of claim 1 , further comprising memory control circuitry coupled to the SRAM cell and configured to:
write a binary weight value to the SRAM cell; and
provide signals at the first read word line, the second read word line, the third read word line, and the fourth read word line, wherein the signals are indicative of a ternary input value and in response to the signals at the first read word line, the second read word line, the third read word line, and the fourth read word line the SRAM cell is configured to provide a signal at the read bit line indicative of a ternary output value at the read bit line.

3. The SRAM system of claim 2 , wherein writing the binary weight value to the SRAM cell comprises:
providing a signal indicative of the binary weight value at the first write bit line; and
providing an activation signal at the write word line.

4. The SRAM system of claim 3 , further comprising analog-to-digital converter (ADC) circuitry coupled to the read bit line and configured to receive the signal indicative of the ternary output value and provide a digital output signal representative of the ternary output value.

5. The SRAM system of claim 4 , wherein the first switching element and the second switching element are transistors.

6. A static random-access memory (SRAM) system comprising a plurality of SRAM cells, each SRAM cell comprising:
a write word line;
a first write bit line and a second write bit line;
a read bit line;
a first read word line, a second read word line, a third read word line, and a fourth read word line;
a first inverter comprising an input coupled to a first intermediate node, an output coupled to a second intermediate node, a first voltage input node coupled to a supply voltage, and a second voltage input node coupled to a fixed voltage;
a second inverter comprising an input coupled to the second intermediate node, an output coupled to the first intermediate node, a first voltage input node coupled to the supply voltage, and a second voltage input node coupled to a fixed voltage;
a third inverter comprising an input coupled to the first intermediate node, an output coupled to the read bit line, a first voltage input node coupled to the first read word line, and a second voltage input node coupled to the second read word line;
a fourth inverter comprising an input coupled to the second intermediate node, an output coupled to the read bit line, a first voltage input node coupled to the third read word line, and a second voltage input node coupled to the fourth read word line;
a first switching element comprising a control node coupled to the write word line, a first switching node coupled to the first write bit line, and a second switching node coupled to the first intermediate node; and
a second switching element comprising a control node coupled to the write word line, a first switching node coupled to the second write bit line, and a second switching node coupled to the second intermediate node.

7. The SRAM system of claim 6 , further comprising memory control circuitry coupled to each of the plurality of SRAM cells and configured to:
write a binary weight value to each one of the plurality of SRAM cells; and
provide signals at the first read word line, the second read word line, the third read word line, and the fourth read word line, wherein the signals are indicative of a ternary input value and in response to the signals at the first read word line, the second read word line, the third read word line, and the fourth read word line each one of the plurality of SRAM cells is configured to provide a signal at the read bit line indicative of a ternary output value at the read bit line.

8. The SRAM system of claim 7 , wherein writing the binary weight value to each one of the plurality of SRAM cells comprises:
providing a signal indicative of the binary weight value at the first write bit line; and
providing an activation signal at the write word line.

9. The SRAM system of claim 7 , further comprising analog-to-digital converter (ADC) circuitry coupled to the read bit line and configured to receive the signal indicative of the ternary output value from each one of the plurality of SRAM cells and provide a digital output signal representative of a bitwise count of the ternary output values of the plurality of SRAM cells.

10. The SRAM system of claim 6 , wherein the first switching element and the second switching element are transistors.

Assignees

• Univ Arizona State
• Univ Columbia

Inventors

• Seo Jae-Sun
• Yin Shihui
• Jiang Zhewei
• Seok Mingoo

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/082

  modifying the architecture, e.g. adding, deleting or silencing nodes or connections · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title