Internal commands for access operations

Patent metadata

Field	Value
Publication number	US-11726716-B2
Application number	US-202117469365-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Mar 4, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Methods, systems, and devices for internal commands for access operations are described. A memory sub-system can receive a request to perform an access operation. A first core of the memory sub-system can generate an internal command for performing the access operation. The internal command can include information for storing in a reference queue of the memory sub-system and an identification of a command entry of the reference queue. The first core can issue the internal command to perform the access operation and a second core of the memory sub-system can store the information in the command entry of the reference queue.

First claim

What is claimed is:

1. A method, comprising:
generating an internal command for performing an access operation on a memory device based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue of the memory device and is associated with at least one command entry in the queue that is allocated for the internal command;
issuing the internal command to perform the access operation on the memory device based at least in part on generating the internal command; and
storing the information in a command entry of the queue based at least in part on issuing the internal command.

2. The method of claim 1 , further comprising:
identifying a message comprising an indicator of the command entry in the queue and a status of the access operation; and
determining whether the access operation was successfully performed based at least in part on identifying the message.

3. The method of claim 2 , further comprising:
determining that the access operation was not successfully performed;
identifying one or more errors associated with the access operation based at least in part on determining that the access operation was not performed successfully; and
correcting the one or more errors associated with the access operation based at least in part on identifying the one or more errors associated with the access operation.

4. The method of claim 3 , further comprising:
issuing, for a second time, the internal command to perform the access operation on the memory device based at least in part on correcting the one or more errors associated with the access operation.

5. The method of claim 1 , wherein the memory device comprises:
a plurality of first cores for communicating with a host system; and
a plurality of second cores for communicating with one or more components internal to the memory device, wherein the internal command is generated and issued by one or more second cores of the plurality of second cores.

6. A method, comprising:
generating an internal command for performing an access operation on a memory device based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue of the memory device, wherein the internal command for performing the access operation comprises an identification of a command entry of the queue and a read command or a write command;
issuing the internal command to perform the access operation on the memory device based at least in part on generating the internal command; and
storing the information in the command entry of the queue based at least in part on issuing the internal command.

7. An apparatus, comprising:
a memory array; and
a controller coupled with the memory array, wherein the controller is operable to cause the apparatus to:
generate an internal command for performing an access operation on the memory array based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue associated with the memory array, wherein the internal command for performing the access operation comprises an identification of a command entry of the queue and a read command or a write command;
issue the internal command to perform the access operation on the memory array based at least in part on generating the internal command; and
store the information in the command entry of the queue based at least in part on issuing the internal command.

8. An apparatus, comprising:
a memory array; and
a controller coupled with the memory array, wherein the controller is operable to cause the apparatus to:
generate an internal command for performing an access operation on the memory array based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue associated with the memory array and is associated with at least one command entry in the queue that is allocated for the internal command;
issue the internal command to perform the access operation on the memory array based at least in part on generating the internal command; and
store the information in a command entry of the queue based at least in part on issuing the internal command.

9. The apparatus of claim 8 , wherein the controller is operable to cause the apparatus to:
identify a message comprising an indicator of the command entry in the queue and a status of the access operation; and
determine whether the access operation was successfully performed based at least in part on identifying the message.

10. The apparatus of claim 9 , wherein the controller is operable to cause the apparatus to:
determine that the access operation was not successfully performed;
identify one or more errors associated with the access operation based at least in part on determining that the access operation was not performed successfully; and
correct the one or more errors associated with the access operation based at least in part on identifying the one or more errors associated with the access operation.

11. The apparatus of claim 10 , wherein the controller is operable to cause the apparatus to:
issue, for a second time, the internal command to perform the access operation on the memory array based at least in part on correcting the one or more errors associated with the access operation.

12. The apparatus of claim 8 , further comprising:
a plurality of first cores associated with the memory array, wherein the plurality of first cores are for communicating with a host system; and
a plurality of second cores for communicating with the memory array, wherein the internal command is generated and issued by one or more second cores of the plurality of second cores.

13. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory device, cause the memory device to:
generate an internal command for performing an access operation on the memory device based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue of the memory device, wherein the internal command for performing the access operation comprises an identification of a command entry of the queue and a read command or a write command;
issue the internal command to perform the access operation on the memory device based at least in part on generating the internal command; and
store the information in the command entry of the queue based at least in part on issuing the internal command.

14. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory device, cause the memory device to:
generate an internal command for performing an access operation on the memory device based at least in part on receiving a command, wherein the internal command comprises information for storing in a queue of the memory device and is associated with at least one command entry in the queue that is allocated for the internal command;
issue the internal command to perform the access operation on the memory device based at least in part on generating the internal command; and
store the information in a command entry of the queue based at least in part on issuing the internal command.

15. The non-transitory computer-readable medium of claim 14 , wherein the instructions, when executed by the processor of the memory device, further cause the memory device to:
identifying a message comprising an indicator of the command entry in the queue and a status of the access operation; and
determining whether the a

Assignees

• Micron Technology Inc

Inventors

• Traver John
• Zhao Ning
• Geukens Tom V
• Li Yun

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title