Coherency locking schemes

Patent metadata

Field	Value
Publication number	US-11726669-B2
Application number	US-202217703818-A
Country	US
Kind code	B2
Filing date	Mar 24, 2022
Priority date	Mar 4, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Methods, systems, and devices for coherency locking are described in which different types of writes have different coherency locking schemes. The types of writes can be associated with different sources of write commands, such as external commands from a host system or internal commands from a garbage collection procedure. Coherency locking can be performed for external write commands received from a host system, while coherency locking is not performed for internal write commands. If an internal write is received for data that has been previously written at a prior location, a write to one or more physical memory devices can be performed and, once an acknowledgment is received that the write is complete, an update to a mapping table with the new location of the data is performed.

First claim

What is claimed is:

1. An apparatus comprising:
a coherency block configured to perform one or more coherency locking operations for preventing read operations at one or more memory cells;
a write manager coupled with the coherency block, the write manager comprising a first processing core configured to perform a write operation and transmit a coherency lock indication to the coherency block based at least in part on the write operation, wherein the write manager is configured to perform a second write operation and refrain from transmitting the coherency lock indication to the coherency block based at least in part on the second write operation being associated with a garbage collection operation; and
a read manager coupled with the coherency block, the read manager comprising a second processing core configured to verify that a coherency is locked at the coherency block and refrain from performing a read operation based at least in part on the coherency being locked.

2. The apparatus of claim 1 , wherein the read manager is configured to verify that the coherency is unlocked at the coherency block and perform the read operation based at least in part on the coherency being unlocked.

3. The apparatus of claim 1 , further comprising:
a logical to physical address table configured to store an updated mapping between a logical address associated with the second write operation and a physical address associated with the second write operation based at least in part on a completion of the second write operation.

4. The apparatus of claim 1 , further comprising:
one or more processing units coupled with the coherency block, the one or more processing units configured to determine that the coherency is locked at the coherency block and perform an access operation at the one or more memory cells based on the coherency being locked.

5. An apparatus comprising:
a coherency block configured to perform one or more coherency locking operations for preventing read operations at one or more memory cells;
a write manager coupled with the coherency block, the write manager comprising a first processing core configured to perform a write operation and transmit a coherency lock indication to the coherency block based at least in part on the write operation;
a read manager coupled with the coherency block, the read manager comprising a second processing core configured to verify that a coherency is locked at the coherency block and refrain from performing a read operation based at least in part on the coherency being locked; and
a garbage collection manager coupled with the write manager, the garbage collection manager configured to refrain from performing the one or more coherency locking operations for preventing the read operations at the one or more memory cells based at least in part on one or more write operations being associated with a garbage collection operation.

6. A method, comprising:
receiving a first write command comprising data associated with a first memory cell;
generating, as part of a media management operation, a second write command to write the data to a second memory cell; and
refraining, during a first duration, from locking a coherency of the first memory cell based at least in part on generating the second write command as part of the media management operation, wherein one or more read operations are performed on the first memory cell during the first duration based at least in part on refraining from locking the coherency of the first memory cell.

7. The method of claim 6 , further comprising:
locking, during a second duration, the coherency of the first memory cell to prevent the one or more read operations at the first memory cell during the second duration based at least in part on receiving the first write command;
writing the data to the first memory cell during the second duration based at least in part on locking the coherency of the first memory cell; and
unlocking the coherency of the first memory cell to allow the one or more read operations at the first memory cell during the first duration based at least in part on writing the data to the first memory cell.

8. The method of claim 7 , further comprising:
storing, as part of the media management operation, the data in the second memory cell based at least in part on generating the second write command; and
reading the data from the first memory cell based at least in part on refraining from locking the coherency of the first memory cell.

9. The method of claim 8 , further comprising:
performing a garbage collection operation on the first memory cell, wherein the garbage collection operation comprises the second write command.

10. The method of claim 7 , wherein receiving the first write command comprises:
receiving the first write command from a host device, wherein locking the coherency of the first memory cell is based at least in part on receiving the first write command from the host device.

11. The method of claim 7 , further comprising:
updating, responsive to completing a write operation associated with the second write command, a mapping record to indicate the data is located at the second memory cell, wherein the mapping record indicates that the data is located at the first memory cell prior to the updating.

12. The method of claim 11 , further comprising:
updating, responsive to receiving the first write command, the mapping record to indicate the data is located at the first memory cell.

13. The method of claim 12 , further comprising:
receiving a read command to read the data from the first memory cell; and
transmitting, to a host device, a coherency lock indication responsive to the read command, wherein the coherency lock indication notifies the host device that the coherency is locked at the first memory cell.

14. The method of claim 11 , further comprising:
receiving, prior to the updating the mapping record responsive to completing the write operation associated with the second write command, a read command to read the data from the first memory cell;
transmitting, to a host device, a coherency lock indication responsive to the read command, wherein the coherency lock indication notifies the host device that the coherency is unlocked at the first memory cell; and
reading the data from the first memory cell based at least in part on the coherency being unlocked at the first memory cell.

15. The method of claim 7 , wherein locking the coherency comprises:
transmitting, to a coherency block of a controller, a coherency lock command and a memory address for the first memory cell to prevent the one or more read operations at the first memory cell.

16. A system comprising:
a plurality of memory components; and
a processing device operatively coupled with the plurality of memory components, the processing device configured to:
receive a first write command comprising data associated with a first memory cell;
generate, as part of a media management operation, a second write command to write the data to a second memory cell; and
refrain, during a first duration, from locking a coherency of the first memory cell based at least in part on generating the second write command as part of the media management operation, wherein refraining from locking the coherency of the first memory cell allows one or more read operations, during the first duration, at the first memory cell.

17. The system of claim 16 , wherein the processing device is further configured to:
lock, during a second duration, the coherency of the first memory cell to prevent the one or mo

Assignees

• Micron Technology Inc

Inventors

• Li Yun
• Traver John

Classifications

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/064

  Management of blocks · CPC title