Techniques for flexible physical drive expansion using a loop back connection

Patent metadata

Field	Value
Publication number	US-11726660-B1
Application number	US-202217721785-A
Country	US
Kind code	B1
Filing date	Apr 15, 2022
Priority date	Apr 15, 2022
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Techniques providing connectivity between a CPU and physical storage devices (PDs) can use a loop back path formed between two connectors of an extended PO slot when an extended I/O card is inserted therein. The two connectors can include a first connector having connectivity with the CPU over a first set of lanes, and a second connector having connectivity with the PDs over a second set of lanes. While the extended I/O card is inserted into the I/O slot, connectivity can be provided between the CPU and the PDs using connectivity provided between the CPU and the first connector and the first set of lanes; using the loop back path provided between the first and second connectors; and using connectivity provided between the second connector and the PDs over the second set of lanes.

First claim

What is claimed is:

1. A system comprising:
one or more physical storage devices;
a central processing unit (CPU); and
an I/O slot including a first connector and a second connector, wherein the first connector is configured to have connectivity with the CPU over a first set of lanes, wherein the second connector is configured to have connectivity with the one or more physical devices over one or more connections configured from a second set of lanes between the second connector and the one or more physical storage devices, wherein the I/O slot is configured to receive an I/O card, and wherein, while the I/O card is inserted into the I/O slot, the I/O card is configured to:
have connectivity to the first connector and the second connector, and
provide connectivity of a loop back path between the first connector and the second connector; and wherein, while the I/O card is inserted into the I/O slot, the system is configured to:
provide connectivity between the CPU and the one or more physical storage devices over the first set of lanes between the CPU and the first connector of the I/O slot, over the loop back path between the first connector and the second connector, and over the second set of lanes between the second connector and the one or more physical storage devices.

2. The system of claim 1 , wherein the one or more physical storage devices do not have connectivity to the CPU when the I/O card is not inserted into the I/O slot.

3. The system of claim 1 , wherein the one or more connections and the second set of lanes are provided, at least in part over a cable.

4. The system of claim 3 , wherein the cable connects the second connector of the I/O slot to a cable connector of an interconnect module, wherein the cable connector of the interconnect module is configured to have connectivity to the one or more physical storage devices.

5. The system of claim 1 , wherein the one or more connections and the second set of lanes are provided, at least in part, over one or more electrically conductive pathways of one or more printed circuit boards.

6. The system of claim 1 , wherein the I/O card is an extended I/O card, the I/O slot is an extended I/O slot, and wherein the I/O slot is further configured to receive a second I/O card different from the I/O card, and
wherein the second I/O card, when inserted into the I/O slot, is configured to use the first connector to have connectivity to the CPU over the first set of lanes, is not configured to use the second connector, and is not configured to have connectivity over the second set of one or more lanes between the I/O slot and the one or more physical storage devices.

7. The system of claim 6 , wherein when the I/O card is inserted into the I/O slot, the I/O card is configured to use the first connector to provide connectivity with the CPU over the first set of one or more lanes.

8. The system of claim 6 , wherein the I/O card includes one or more components configured to be connectively disposed between the first connector and the second connector of the I/O slot.

9. The system of claim 8 , wherein the one or more components includes an intervening switch configured to be connectively disposed between the first connector and the second connector of the I/O slot.

10. The system of claim 9 , wherein the intervening switch is configured to have connectivity to the CPU and to the one or more physical storage devices, wherein the intervening switch has connectivity to the one or more physical storage devices over the second connector and the one or more connections configured from the second set of lanes, and wherein the intervening switch has connectivity to the CPU over the first connector and the first set of lanes.

11. The system of claim 10 , wherein the intervening switch is configured to route packets between the second set of lanes and the first set of lanes.

12. The system of claim 11 , wherein X1 denotes a number of lanes in the first set of lanes, X2 denotes a number of lanes in the second set of lanes, and wherein X2 is more than X1.

13. The system of claim 8 , wherein the one or more components include an intervening retimer configured to be connectively disposed between the first connector and the second connector of the I/O slot.

14. The system of claim 13 , wherein the intervening retimer is configured to have connectivity to the CPU and to the one or more physical storage devices, wherein the intervening retimer has connectivity to the one or more physical storage devices over the second connector and the second one or more connections configured from the second set of lanes, and wherein the intervening retimer has connectivity to the CPU over the first connector and the first set of lanes.

15. The system of claim 14 , wherein X1 denotes a number of lanes in the first set of lanes, X2 denotes a number of lanes in the second set of lanes, and wherein X2 is equal to X1.

16. A method for providing connectivity to one or more physical storage devices in a system comprising:
providing connectivity between a central processing unit (CPU) and an I/O slot over a first set of lanes connecting the CPU and a first connector of the I/O slot;
providing connectivity over a second set of lanes between a second connector of the I/O slot and the one or more physical storage devices;
inserting an I/O card into the I/O slot whereby the I/O card has connectivity to the first connector and the second connector of the I/O slot;
responsive to said inserting the I/O card into the I/O slot whereby the I/O card has connectivity to the first connector and the second connector of the I/O slot, performing processing including:
providing, using the I/O card and the I/O slot, a loop back path between the first connector of the I/O slot and the second connector of the I/O slot; and
providing, by the system, connectivity between the CPU and the one or more physical storage devices over the first set of lanes between the CPU and the first connector of the I/O slot, over the loop back path between the first connector and the second connector, and over the second set of lanes between the second connector and the one or more physical storage devices.

17. The method of claim 16 , wherein the system is a data storage system including an enclosure, wherein the enclosure includes the CPU, the one or more physical storage devices, and a cable used to provide, at least in part, the second set of lanes between the second connector of the I/O slot and the one or more physical storage devices.

18. The method of claim 16 , wherein the second set of lanes is configured into one or more connections, wherein each of the one or more connections includes one or more of the second set of lanes, and wherein each of the one or more connections is a connection to an associated one of the one or more physical storage devices.

Assignees

• Dell Products Lp

Inventors

• Hadav Aric
• Dibb Thomas N
• Alkalay Amitai

Classifications

• G06F3/0635

  by changing the path, e.g. traffic rerouting, path reconfiguration · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0613 Primary

  in relation to throughput · CPC title

• G06F3/0673

  Single storage device · CPC title