Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via

Patent metadata

Field	Value
Publication number	US-11723282-B2
Application number	US-202117231419-A
Country	US
Kind code	B2
Filing date	Apr 15, 2021
Priority date	Jun 13, 2019
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode, and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure, and a first dielectric layer surrounding the spacers. The MRAM device further includes a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the MRAM device includes a second dielectric layer on the patterned etch stop layer, and a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer.

First claim

What is claimed is:

1. A magnetic random access memory (MRAM) device, comprising:
a bottom electrode over a substrate;
a magnetic tunnel junction (MTJ) structure on the bottom electrode;
a top electrode on the MTJ structure;
spacers on sidewalls of the top electrode and the MTJ structure;
a first dielectric layer surrounding the spacers;
a patterned etch stop layer on the first dielectric layer and the spacers;
a second dielectric layer on the patterned etch stop layer; and
a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer, wherein the top electrode via has a lower portion overlapping and in direct contact with a top surface and a sidewall of the patterned etch stop layer and an upper portion in direct contact with a sidewall of the second dielectric layer.

2. The MRAM device as claimed in claim 1 , further comprising:
a bottom electrode via under the bottom electrode;
an interlayer dielectric (ILD) layer surrounding the bottom electrode via; and
an etch stop layer on the ILD layer and surrounding the bottom electrode, wherein the etch stop layer and the patterned etch stop layer are made of different materials, and the etch stop layer has a thickness that is greater than the thickness of the patterned etch stop layer.

3. The MRAM device as claimed in claim 1 , wherein the sidewalls of the top electrode are vertically aligned with the sidewalls of the MTJ structure.

4. The MRAM device as claimed in claim 1 , wherein each of the spacers comprises a first spacer in contact with the sidewalls of the top electrode and the MTJ structure, and a second spacer on a sidewall of the first spacer.

5. A magnetic random access memory (MRAM) device, comprising:
a bottom electrode over a semiconductor substrate;
a magnetic tunnel junction (MTJ) structure on the bottom electrode;
a top electrode on the MTJ structure;
a first spacer on sidewalls of the top electrode and the MTJ structure;
a second spacer on sidewalls of the first spacer;
an etch stop layer on the first spacer and the second spacer, wherein the etch stop layer is in direct contact with the first spacer and the second spacer; and
a top electrode via covering the top electrode and a top surface and a sidewall of the etch stop layer.

6. The MRAM device as claimed in claim 5 , wherein a sidewall of the etch stop layer is substantially aligned with a sidewall of the top electrode.

7. The MRAM device as claimed in claim 5 , wherein the top electrode via is in direct contact with the etch stop layer.

8. The MRAM device as claimed in claim 5 , wherein the etch stop layer is made of a high electrical resistance material or a high dielectric constant material.

9. The MRAM device as claimed in claim 5 , wherein the first spacer is L-shaped.

10. The MRAM device as claimed in claim 5 , wherein the first spacer is in direct contact with a bottom surface of the second spacer.

11. The MRAM device as claimed in claim 5 , wherein a width of the bottom electrode is greater than a width of the MTJ structure.

12. The MRAM device as claimed in claim 5 , further comprising:
an interconnect structure between the bottom electrode via and the semiconductor substrate, wherein the interconnect structure comprises a metal line and a conductive via embedded in an intermetal dielectric (IMD) layer, and the metal line electrically connects the bottom electrode via to the semiconductor substrate.

13. A magnetic random access memory (MRAM) device, comprising:
a bottom electrode over a substrate;
a first etch stop layer surrounding the bottom electrode;
a magnetic tunnel junction (MTJ) structure on the bottom electrode;
a top electrode on the MTJ structure;
spacers surrounding the top electrode and the MTJ structure;
a dielectric layer surrounding the spacers and on the first etch stop layer;
a second etch stop layer on the dielectric layer and the spacers, wherein a sidewall of the second etch stop layer protrudes from a sidewall of the dielectric layer, and the second etch stop layer is in direct contact with a topmost surface of the spacers; and
a top electrode via on the top electrode and the etch stop layer.

14. The MRAM device as claimed in claim 13 , wherein a material of the first etch stop layer is different form a material of the second etch stop layer.

15. The MRAM device as claimed in claim 13 , wherein a thickness of the second etch stop layer is less than a thickness of the first etch stop layer.

16. The MRAM device as claimed in claim 13 , wherein an outer sidewall of the spacers protrudes from a sidewall of the bottom electrode.

17. The MRAM device as claimed in claim 13 , wherein the MTJ structure comprises a first ferromagnetic layer over the bottom electrode, an insulating barrier layer over the first ferromagnetic layer, and a second ferromagnetic layer over the insulating barrier layer.

18. The MRAM device as claimed in claim 17 , further comprising:
an anti-ferromagnetic (AFM) layer under the first ferromagnetic layer and above the bottom electrode and the first etch stop layer.

19. The MRAM device as claimed in claim 5 , further comprising:
a dielectric layer in direct contact with the second spacer and the etch stop layer.

20. The MRAM device as claimed in claim 19 , wherein the etch stop layer is higher than the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacuturing Company Ltd

Inventors

• Liao Wei-Hao
• Tien Hsi-Wen
• Lu Chih-Wei
• Dai Pin-Ren
• Lee Chung-Ju

Classifications

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H01F10/3254 Primary

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• H01F41/34

  in patterns, e.g. by lithography · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/80

  Constructional details · CPC title